Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods

Patent metadata

Field	Value
Publication number	US-10840336-B2
Application number	US-201816192897-A
Country	US
Kind code	B2
Filing date	Nov 16, 2018
Priority date	Nov 16, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer. The contact may include at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers, and a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer. The semiconductor portion between the oxygen monolayer and the metal layer may have a dopant concentration of 1×1021 atoms/cm3 or greater.

First claim

That which is claimed is:

1. A semiconductor device comprising:
a semiconductor layer; and
at least one contact in the semiconductor layer and comprising
at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers, and
a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer,
a semiconductor portion between the oxygen monolayer and the metal layer having a dopant concentration of 1×10 21 atoms/cm 3 or greater.

2. The semiconductor device of claim 1 further comprising spaced apart source and drain regions in the semiconductor layer defining a channel region extending therebetween, and a gate overlying the channel region; and wherein the at least one contact comprises at least one of a source contact and a drain contact.

3. The semiconductor device of claim 1 further comprising spaced apart first and second source/drain regions in the semiconductor layer defining a channel region extending therebetween, and a gate overlying the channel region; and wherein the at least one contact overlies at least one of the source and drain regions.

4. The semiconductor device of claim 3 wherein the at least one contact comprises a respective contact overlying each of the source and drain regions.

5. The semiconductor device of claim 1 wherein the metal layer comprises at least one of titanium, cobalt, nickel and platinum.

6. The semiconductor device of claim 1 wherein the semiconductor layer comprises silicon.

7. The semiconductor device of claim 1 wherein adjacent portions of the semiconductor layer above and below the at least one oxygen monolayer each comprises a plurality of stacked base semiconductor monolayers.

8. A semiconductor device comprising:
a silicon layer; and
spaced apart source and drain regions in the silicon layer defining a channel region extending therebetween;
a gate overlying the channel region; and
a respective contact in the silicon layer overlying each of the source and drain regions and comprising
at least one oxygen monolayer constrained within a crystal lattice of adjacent portions of the silicon layer and spaced apart from a surface of the silicon layer by between one and four monolayers, and
a metal layer on the surface of the silicon layer above the at least one oxygen monolayer,
a silicon portion between the oxygen monolayer and the metal layer having a dopant concentration of 1×10 21 atoms/cm 3 or greater.

9. The semiconductor device of claim 8 wherein the metal layer comprises at least one of titanium, cobalt, nickel and platinum.

10. The semiconductor device of claim 8 wherein adjacent portions of the silicon layer above and below the at least one oxygen monolayer each comprises a plurality of stacked base silicon monolayers.

11. A method for making a semiconductor device comprising:
forming at least one contact in a semiconductor layer by
forming at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers,
forming a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer, and
doping a semiconductor portion between the oxygen monolayer and the metal layer to a dopant concentration of 1×10 21 atoms/cm 3 or greater.

12. The method of claim 11 further comprising:
forming spaced apart source and drain regions in the semiconductor layer defining a channel region extending therebetween; and
forming a gate overlying the channel region;
wherein the at least one contact comprises at least one of a source contact and a drain contact.

13. The method of claim 11 further comprising:
forming spaced apart source and drain regions in the semiconductor layer defining a channel region extending therebetween; and
forming a gate overlying the channel region;
wherein the at least one contact comprises a respective contact overlying each of the source and drain regions.

14. The method of claim 11 further comprising:
forming spaced apart source and drain regions in the semiconductor layer defining a channel region extending therebetween; and
forming a gate overlying the channel region;
wherein the at least one contact comprises a body contact.

15. The method of claim 11 wherein the metal layer comprises at least one of titanium, cobalt, nickel and platinum.

16. The method of claim 11 wherein the semiconductor layer comprises silicon.

17. The method of claim 11 wherein adjacent portions of the semiconductor layer above and below the at least one oxygen monolayer each comprises a plurality of stacked base silicon monolayers.

Assignees

• Atomera Inc

Inventors

• Connelly Daniel
• Hytha Marek
• Takeuchi Hideki
• Burton Richard
• Mears Robert J

Classifications

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3202

  Materials thereof · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title