Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance

Patent metadata

Field	Value
Publication number	US-10818755-B2
Application number	US-201816192987-A
Country	US
Kind code	B2
Filing date	Nov 16, 2018
Priority date	Nov 16, 2018
Publication date	Oct 27, 2020
Grant date	Oct 27, 2020

Abstract

A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

First claim

That which is claimed is:

1. A method for making a semiconductor device comprising:
forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, at least one of the source and drain regions being separated into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region, the dopant diffusion blocking superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
forming a gate on the channel region.

2. The method of claim 1 wherein each of the source and drain regions is separated into lower and upper regions by a respective dopant diffusion blocking superlattice.

3. The method of claim 1 further comprising forming a body dopant diffusion blocking superlattice in the semiconductor layer extending between the source and drain regions and comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

4. The method of claim 1 wherein the upper region is level with an upper surface of the semiconductor layer.

5. The method of claim 1 wherein the upper region is raised above an upper surface of the semiconductor layer.

6. The method of claim 1 wherein the lower region comprises a different material than the upper region.

7. The method of claim 6 wherein the lower region comprises silicon and the upper region comprises silicon germanium.

8. The method of claim 6 wherein the lower region comprises silicon germanium and upper region comprises silicon.

9. The method of claim 1 further comprising forming a metal contact on the upper region.

10. The method of claim 9 wherein the metal contact comprises at least one of titanium, cobalt, nickel and platinum.

11. The method of claim 1 wherein the base semiconductor monolayers comprise silicon.

12. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

13. A method for making a semiconductor device comprising:
forming spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, the source region comprising a source dopant diffusion blocking superlattice extending through the source region to separate the source region into a lower source region and an upper source region with the upper source region having a same conductivity and higher dopant concentration than the lower source region, and the drain region comprising a drain dopant diffusion blocking superlattice extending through the drain region to separate the drain region into a lower drain region and an upper drain region with the upper drain region having a same conductivity and higher dopant concentration than the lower drain region;
each of the source dopant diffusion blocking superlattice and drain dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
forming a gate on the channel region;
wherein the upper drain region and upper source region are each level with an upper surface of the semiconductor layer.

14. The method of claim 13 wherein the base semiconductor monolayers comprise silicon.

15. The method of claim 13 wherein the at least one non-semiconductor monolayer comprises oxygen.

16. A method for making a semiconductor device comprising:
forming spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, the source region comprising a source dopant diffusion blocking superlattice extending through the source region to separate the source region into a lower source region and an upper source region with the upper source region having a same conductivity and higher dopant concentration than the lower source region, the drain region comprising a drain dopant diffusion blocking superlattice extending through the drain region to separate the drain region into a lower drain region and an upper drain region with the upper drain region having a same conductivity and higher dopant concentration than the lower drain region;
each of the source dopant diffusion blocking superlattice and drain dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
forming a gate on the channel region;
wherein the upper drain region and upper source region are each raised above an upper surface of the semiconductor layer.

17. The method of claim 16 wherein the lower drain region comprises a different material than the upper drain region; and the lower source region comprises a different material than the upper source region.

18. The method of claim 17 wherein the lower source and drain regions comprise silicon; and wherein the upper source and drain regions comprise silicon germanium.

19. The method of claim 17 wherein the lower source and drain regions comprise silicon germanium; and wherein the upper source and drain regions comprise silicon.

20. The method of claim 16 further comprising forming a metal source contact on the upper source region, and a metal drain contact on the upper drain region.

21. The method of claim 20 wherein the metal source and drain contacts comprise at least one of titanium, cobalt, nickel and platinum.

Assignees

• Atomera Inc

Inventors

• Takeuchi Hideki
• Connelly Daniel
• Hytha Marek
• Burton Richard
• Mears Robert J

Classifications

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/209

  in silicon to make buried insulating layers · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title