Semiconductor devices with enhanced deterministic doping and related methods
US-2017294514-A1 · Oct 12, 2017 · US
Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice
US10249745B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10249745-B2 |
| Application number | US-201715670240-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 7, 2017 |
| Priority date | Aug 8, 2016 |
| Publication date | Apr 2, 2019 |
| Grant date | Apr 2, 2019 |
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Abstract
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A method for making a semiconductor device may include forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and forming a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor layer, and forming a second doped semiconductor layer on the second superlattice layer.
First claim
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That which is claimed is: 1. A method for making a semiconductor device comprising: forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, forming a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor layer, and forming a second doped semiconductor layer on the second barrier layer. 2. The method of claim 1 wherein the first and second doped semiconductor layers each comprises silicon, and wherein the intrinsic layer comprises germanium. 3. The method of claim 1 wherein the second barrier layer comprises a second superlattice, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. 4. The method of claim 3 wherein the second doped semiconductor layer comprises a single crystal semiconductor layer. 5. The method of claim 1 wherein the second barrier layer comprises an oxide layer. 6. The method of claim 5 wherein the second doped semiconductor layer comprises a polycrystalline semiconductor layer. 7. The method of claim 1 wherein the first and second doped semiconductor layers have a same dopant conductivity type. 8. The method of claim 1 wherein the first and second doped semiconductor layers have opposite dopant conductivity types. 9. The method of claim 1 wherein forming the at least one DBRTD comprises forming a pair of DBRTDs connected in series to define a monostable-bistable transition logic element (MOBILE). 10. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen, and wherein the plurality of stacked base semiconductor monolayers each comprises silicon. 11. A method for making a semiconductor device comprising: forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, forming a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor, the second barrier layer comprising a second superlattice, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions and forming a second doped semiconductor layer on the second barrier layer. 12. The method of claim 11 wherein the first and second doped semiconductor layers each comprises silicon, and wherein the intrinsic layer comprises germanium. 13. The method of claim 11 wherein the second doped semiconductor layer comprises a single crystal semiconductor layer. 14. The method of claim 11 wherein the first and second doped semiconductor layers have a same dopant conductivity type. 15. The method of claim 11 wherein the first and second doped semiconductor layers have opposite dopant conductivity types. 16. The method of claim 11 wherein forming the at least one DBRTD comprises forming a pair of DBRTDs connected in series to define a monostable-bistable transition logic element (MOBILE). 17. A method for making a semiconductor device comprising: forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, forming a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor layer comprising an oxide layer, and forming a second doped semiconductor layer on the second barrier layer. 18. The method of claim 17 wherein the first and second doped semiconductor layers each comprises silicon, and wherein the intrinsic layer comprises germanium. 19. The method of claim 17 wherein the second doped semiconductor layer comprises a polycrystalline semiconductor layer. 20. The method of claim 17 wherein the first and second doped semiconductor layers have a same dopant conductivity type. 21. The method of claim 17 wherein the first and second doped semiconductor layers have opposite dopant conductivity types. 22. The method of claim 17 wherein forming the at least one DBRTD comprises forming a pair of DBRTDs connected in series to define a monostable-bistable transition logic element (MOBILE).
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US10249745B2 cover?
- A method for making a semiconductor device may include forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and forming a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers …
- Who is the assignee on this patent?
- Atomera Inc
- What technology area does this patent fall under?
- Primary CPC classification H01L29/7376. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 02 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).