Semiconductor devices with superlattice and punch-through stop (pts) layers at different depths and related methods

Patent metadata

Field	Value
Publication number	US-2016336406-A1
Application number	US-201615154276-A
Country	US
Kind code	A1
Filing date	May 13, 2016
Priority date	May 15, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, and the first PTS layer may be at a first depth below the first channel. The semiconductor device may further include second transistors having a second operating voltage higher than the first operating voltage. Each second transistor may include a second channel and a second PTS layer in the semiconductor substrate, and the second PTS layer may be at a second depth below the second channel that is greater than the first depth. Furthermore, the first channel may include a first superlattice, and the second channel may include a second superlattice.

First claim

That which is claimed is:

1 . A semiconductor device comprising:
a semiconductor substrate; a plurality of first transistors having a first operating voltage, each first transistor comprising a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, the first PTS layer being at a first depth below the first channel; and a plurality of second transistors having a second operating voltage higher than the first operating voltage, each second transistor comprising a second channel and a second PTS layer in the semiconductor substrate, the second PTS layer being at a second depth below the second channel and being greater than the first depth; the first channel comprising a first superlattice, and the second channel comprising a second superlattice.

2 . The semiconductor device of claim 1 wherein the first and second superlattices each comprises a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

3 . The semiconductor device of claim 2 wherein each base semiconductor portion comprises silicon.

4 . The semiconductor device of claim 2 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

5 . The semiconductor device of claim 2 wherein the at least one non-semiconductor layer comprises oxygen.

6 . The semiconductor device of claim 1 wherein the plurality of first transistors comprises a plurality of core transistors, and the plurality of second transistors comprises a plurality of input/output transistors.

7 . The semiconductor device of claim 1 wherein the first and second PTS layers each comprises a highly doped semiconductor layer.

8 . The semiconductor device of claim 1 wherein the first channel comprises an adjacent first portion of the semiconductor substrate below the first superlattice, and the second channel comprises an adjacent second portion of the semiconductor substrate below the second superlattice.

9 . The semiconductor device of claim 1 wherein each of the first transistors comprises a first gate overlying the first channel, and spaced apart first source and drain regions on opposite sides of the first gate; and wherein each of the second transistors comprises a second gate overlying the second channel, and spaced apart second source and drain regions on opposite sides of the second gate.

10 . A semiconductor device comprising:
a semiconductor substrate; a plurality of first transistors having a first operating voltage, each first transistor comprising a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, the first PTS layer being at a first depth below the first channel; and a plurality of second transistors having a second operating voltage higher than the first operating voltage, each second transistor comprising a second channel and a second PTS layer in the semiconductor substrate, the second PTS layer being at a second depth below the second channel and being greater than the first depth; the first channel comprising a first superlattice, and the second channel comprising a second superlattice; the first and second superlattices each comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; the plurality of first transistors comprising a plurality of core transistors, and the plurality of second transistors comprising a plurality of input/output transistors.

11 . The semiconductor device of claim 10 wherein each base semiconductor portion comprises silicon.

12 . The semiconductor device of claim 10 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

13 . The semiconductor device of claim 10 wherein the at least one non-semiconductor layer comprises oxygen.

14 . The semiconductor device of claim 10 wherein the first and second punch-through stop layers each comprises a highly doped semiconductor layer.

15 . The semiconductor device of claim 10 wherein the first channel comprises an adjacent first portion of the semiconductor substrate below the first superlattice, and the second channel comprises an adjacent second portion of the semiconductor substrate below the second superlattice.

16 . The semiconductor device of claim 10 wherein each of the first transistors comprises a first gate overlying the first channel, and spaced apart first source and drain regions on opposite sides of the first gate; and wherein each of the second transistors comprises a second gate overlying the second channel, and spaced apart second source and drain regions on opposite sides of the second gate.

17 . A method of making a semiconductor device comprising:
forming a plurality of first transistors having a first operating voltage, each first transistor comprising a first channel and a first punch-through stop (PTS) layer in a semiconductor substrate, the first PTS layer being at a first depth below the first channel, and the first channel comprising a first superlattice; and forming a plurality of second transistors having a second operating voltage higher than the first operating voltage, each second transistor comprising a second channel and a second PTS layer in the semiconductor substrate, the second PTS layer being at a second depth below the second channel and being greater than the first depth, and the second channel comprising a second superlattice.

18 . The method of claim 17 wherein the first and second superlattices each comprises a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

19 . The method of claim 18 wherein each base semiconductor portion comprises silicon.

20 . The method of claim 18 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

21 . The method of claim 18 wherein the at least one non-semiconductor layer comprises oxygen.

22 . The method of claim 17 wherein forming the plurality of first transistors comprises forming a plurality of core transistors, and forming the plurality of second transistors comprises forming a plurality of input/output transistors.

23 . The method of claim 17 wherein the first and second punch-through stop layers each comprises a highly doped semiconductor layer.

Assignees

• Atomera Inc

Inventors

• Mears Robert J
• Takeuchi Hideki

Classifications

• H10D84/0156

  Manufacturing their doped wells · CPC title

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/0128 Primary

  Manufacturing their channels · CPC title