Minimizing effects of cache thrashing by altering a persistence policy for non-temporal workloads
US-2026072836-A1 · Mar 12, 2026 · US
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Walters Craig R patents
Walters Craig R is listed as an inventor on 70 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Walters Craig R |
| Total patents | 70 |
| First publication | Feb 26, 2015 |
| Latest publication | Mar 12, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Altering processing characteristics based on thermal data
US-2026050493-A1 · Feb 19, 2026 · US
Detecting and mitigating false structure sharing within a cache line
US-2025370933-A1 · Dec 4, 2025 · US
Controlling speculative actions based on a hit/miss predictor
US-12487825-B2 · Dec 2, 2025 · US
Detecting and mitigating false structure sharing within a cache line
US-12487935-B1 · Dec 2, 2025 · US
Controlling speculative actions based on a hit/miss predictor
US-2025272098-A1 · Aug 28, 2025 · US
Staggered three-dimensional chip stacking
US-2025275250-A1 · Aug 28, 2025 · US
Instruction execution scheduling using a hit/miss predictor
US-12288075-B1 · Apr 29, 2025 · US
Real-time snoop status
US-2025077430-A1 · Mar 6, 2025 · US
Using a predetermined bit to represent a predetermined pattern in a cache line
US-2024202117-A1 · Jun 20, 2024 · US
Recent patents
Latest publications not already listed above.
Serialized broadcast command messaging in a distributed symmetric multiprocessing (smp) system
US-2024061803-A1 · Feb 22, 2024 · US
Fast memory clear of system memory
US-2024053897-A1 · Feb 15, 2024 · US
Lateral persistence directory states
US-11620231-B2 · Apr 4, 2023 · US
Lateral persistence directory states
US-2023054424-A1 · Feb 23, 2023 · US
Multiple copy scoping bits for cache memory
US-11487672-B1 · Nov 1, 2022 · US
Controller address contention assumption
US-11461151-B2 · Oct 4, 2022 · US
Efficient generation of instrumentation data for direct memory access operations
US-11099966-B2 · Aug 24, 2021 · US
Controller address contention assumption
US-2021240548-A1 · Aug 5, 2021 · US
Efficient generation of instrumentation data for direct memory access operations
US-2021216430-A1 · Jul 15, 2021 · US
Controller address contention assumption
US-11010210-B2 · May 18, 2021 · US
Controller address contention assumption
US-2021034438-A1 · Feb 4, 2021 · US
Accuracy sensitive performance counters
US-10884890-B2 · Jan 5, 2021 · US
Memory state indicator check operations
US-10884945-B2 · Jan 5, 2021 · US
Memory state indicator check operations
US-10884946-B2 · Jan 5, 2021 · US
Speculative data return concurrent to an exclusive invalidate request
US-10795824-B2 · Oct 6, 2020 · US
Concurrent modification of shared cache line by multiple processors
US-10769068-B2 · Sep 8, 2020 · US
Conditional memory spreading for heterogeneous memory sizes
US-10684968-B2 · Jun 16, 2020 · US
Speculative data return concurrent to an exclusive invalidate request
US-2020159665-A1 · May 21, 2020 · US
Memory state indicator
US-10635308-B2 · Apr 28, 2020 · US
Memory state indicator
US-10635307-B2 · Apr 28, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 70 |
| Drapala Garrett M | 1 |
| Mak Pak-Kin | 1 |
| O'Neill Jr Arthur J | 1 |
| Walters Craig R | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0811 | 20 |
| G06F12/084 | 15 |
| G06F2212/1024 | 12 |
| G06F12/0828 | 9 |
| G06F3/0673 | 9 |