Fast memory clear of system memory

Patent metadata

Field	Value
Publication number	US-2024053897-A1
Application number	US-202217818630-A
Country	US
Kind code	A1
Filing date	Aug 9, 2022
Priority date	Aug 9, 2022
Publication date	Feb 15, 2024
Grant date	—

Abstract

Various embodiments are provided herein for clearing memory of system in a computing environment. A zero-filled cache line with a single z-bit per entry in the cache directory may be defined. The “z” is a positive integer. A plurality of instruction set architecture (“ISA”) instructions are provided with a single z-bit in a cache line as defined in a cache directory to clear an entire cache line.

First claim

1 . A method for clearing of memory of a computing system in a computing environment by one or more processors comprising:
setting, by one or more of a plurality of instruction set architecture (“ISA”) instructions, a single bit as defined in a cache directory to clear an entire cache line.

2 . The method of claim 1 , further including defining a zero-filled cache line according to a value of the single bit per entry in the cache directory.

3 . The method of claim 1 , further including exchanging a cache coherency state for clearing the cache line with other caches in the computing system according to a value of the single bit sent to the other caches.

4 . The method of claim 1 , further including exchanging only a cache coherency state among cores of the one or more processors according to a value of the single bit sent to the cores.

5 . The method of claim 1 , further including setting the single bit in one or more sequential sets of cache lines in the cache directory by commanding a clear-machine to clear the one or more sequential sets of cache lines by the plurality of ISA instructions.

6 . The method of claim 1 , further including setting the single bit to a value of zero when the cache line is written over by non-zeros.

7 . The method of claim 1 , further including using a clear machine unit to clear a plurality of bits in the cache directory.

8 . A system for clearing of memory of a computing system in a computing environment, comprising:
one or more computers with executable instructions that when executed cause the system to:
set, by one or more of a plurality of instruction set architecture (“ISA”) instructions, a single bit as defined in a cache directory to clear an entire cache line.

9 . The system of claim 8 , wherein the executable instructions when executed cause the system to define a zero-filled cache line according to a value of the single bit per entry in the cache directory.

10 . The system of claim 8 , wherein the executable instructions when executed cause the system to exchange a cache coherency state for clearing the cache line with other caches in the computing system according to a value of the single bit sent to the other caches.

11 . The system of claim 8 , wherein the executable instructions when executed cause the system to exchange only a cache coherency state among cores of the one or more processors according to a value of the single bit sent to the cores.

12 . The system of claim 8 , wherein the executable instructions when executed cause the system to set the single bit in one or more sequential sets of cache lines in the cache directory by commanding a clear-machine to clear the one or more sequential sets of cache lines by the plurality of ISA instructions.

13 . The system of claim 8 , wherein the executable instructions when executed cause the system to set the single bit to a value of zero when the cache line is written over by non-zeros.

14 . The system of claim 8 , wherein the executable instructions when executed cause the system to use a clear machine unit to clear a plurality of bits in the cache directory.

15 . A computer program product for clearing of memory of a computing system in a computing environment, the computer program product comprising:
one or more non-transitory computer readable storage media, and program instructions collectively stored on the one or more non-transitory computer readable storage media, the program instructions comprising: program instructions to set, by one or more of a plurality of instruction set architecture (“ISA”) instructions, a single bit as defined in a cache directory to clear an entire cache line.

16 . The computer program product of claim 15 , further including program instructions to define a zero-filled cache line according to a value of the single bit per entry in the cache directory.

17 . The computer program product of claim 15 , further including program instructions to exchange a cache coherency state for clearing the cache line with other caches in the computing system according to a value of the single bit sent to the other caches.

18 . The computer program product of claim 15 , further including program instructions to set the single bit in one or more sequential sets of cache lines in the cache directory by commanding a clear-machine to clear the one or more sequential sets of cache lines by the plurality of ISA instructions.

19 . The computer program product of claim 15 , further including program instructions to set the single bit to a value of zero when the cache line is written over by non-zeros.

20 . The computer program product of claim 15 , further including program instructions to use a clear machine unit to clear a plurality of bits in the cache directory.

Assignees

• IBM

Inventors

• Abali Bulent
• Buyuktosunoglu Alper
• Walters Craig R
• Tzortzatos Elpida
• Blaner Bartholomew

Classifications

• G06F3/0613 Primary

  in relation to throughput · CPC title

• G06F3/0671

  In-line storage system · CPC title

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F2212/60

  Details of cache memory · CPC title