Detecting and mitigating false structure sharing within a cache line

Patent metadata

Field	Value
Publication number	US-12487935-B1
Application number	US-202418731468-A
Country	US
Kind code	B1
Filing date	Jun 3, 2024
Priority date	Jun 3, 2024
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

Examples described herein provide a computer-implemented method that includes generating an extended hot line table that tracks cross-core contended cache lines for multiple processors of a processing system based on cache requests, the extended hot line table storing at least metadata for a cross-core contended cache line. The method further includes polling, using firmware, the extended hot line table in each of the multiple processors of the processing system to identify contention information. The method further includes aggregating the contention information from each of the multiple processors to generate aggregated contention information. The method further includes processing subsequent cache requests using the aggregated contention information.

First claim

What is claimed is:

1. A computer-implemented method comprising:
generating an extended hot line table that tracks cross-core contended cache lines for multiple processors of a processing system based on cache requests, the extended hot line table storing at least metadata for a cross-core contended cache line;
polling, using firmware, the extended hot line table in each of the multiple processors of the processing system to identify contention information;
aggregating the contention information from each of the multiple processors to generate aggregated contention information;
processing subsequent cache requests using the aggregated contention information; and
generating, using the aggregated contention information, a virtual address intercept table.

2. The computer-implemented method of claim 1 , wherein the virtual address intercept table remaps virtual addresses by sub-cache line offsets to independent virtual and absolute address spaces.

3. The computer-implemented method of claim 2 , wherein the virtual address intercept table stores a virtual address, a sub-line offset start value, a sub-line offset end value, an intercept address, and a sub-line offset value.

4. The computer-implemented method of claim 2 , wherein the remapping of virtual addresses by sub-cache line offsets is performed prior to or at program execution.

5. The computer-implemented method of claim 2 , further comprising making results of remapping of virtual addresses by sub-cache line offsets available to a program product.

6. The computer-implemented method of claim 1 , wherein each of the multiple processors comprises multiple cores, and wherein each of the multiple cores includes a dedicated extended hot line table.

7. The computer-implemented method of claim 1 , wherein the metadata is related to hot cache line interactions where such information is made available to a program product.

8. The computer-implemented method of claim 7 , wherein the metadata comprises a relative hotness of sub-cache line segments, types of operations causing cache line contentions, internal core actions taken on the cross-core contended cache lines, and program product accessible interfaces.

9. The computer-implemented method of claim 1 , further comprising making the contention information available to a program product.

10. A system comprising:
a memory comprising computer readable instructions; and
a processing device for executing the computer readable instructions, the computer readable instructions controlling the processing device to perform operations comprising:
generating an extended hot line table that tracks cross-core contended cache lines for multiple processors of a processing system based on cache requests, the extended hot line table storing at least metadata for a cross-core contended cache line;
polling, using firmware, the extended hot line table in each of the multiple processors of the processing system to identify contention information;
aggregating the contention information from each of the multiple processors to generate aggregated contention information;
processing subsequent cache requests using the aggregated contention information; and
generating, using the aggregated contention information, a virtual address intercept table.

11. The system of claim 10 , wherein the virtual address intercept table remaps virtual addresses by sub-cache line offsets to independent virtual and absolute address spaces.

12. The system of claim 11 , wherein the virtual address intercept table stores a virtual address, a sub-line offset start value, a sub-line offset end value, an intercept address, and a sub-line offset value.

13. The system of claim 11 , wherein the remapping of virtual addresses by sub-cache line offsets is performed prior to or at program execution.

14. The system of claim 11 , wherein the operations further comprise making results of remapping of virtual addresses by sub-cache line offsets available to a program product.

15. The system of claim 10 , wherein each of the multiple processors comprises multiple cores, and wherein each of the multiple cores includes a dedicated extended hot line table.

16. The system of claim 10 , wherein the metadata is related to hot cache line interactions where such information is made available to a program product.

17. The system of claim 16 , wherein the metadata comprises a relative hotness of sub-cache line segments, types of operations causing cache line contentions, internal core actions taken on the cross-core contended cache lines, and program product accessible interfaces.

18. The system of claim 10 , wherein the operations further comprise making the contention information available to a program product.

19. A computer program product comprising:
a set of one or more computer-readable storage media;
program instructions, collectively stored in the set of one or more storage media, for causing a processor set to perform the following computer operations:
generating an extended hot line table that tracks cross-core contended cache lines for multiple processors of a processing system based on cache requests, the extended hot line table storing at least metadata for a cross-core contended cache line;
polling, using firmware, the extended hot line table in each of the multiple processors of the processing system to identify contention information;
aggregating the contention information from each of the multiple processors to generate aggregated contention information;
processing subsequent cache requests using the aggregated contention information; and
generating, using the aggregated contention information, a virtual address intercept table.

20. The computer program product of claim 19 , wherein the virtual address intercept table remaps virtual addresses by sub-cache line offsets to independent virtual and absolute address spaces.

Assignees

• IBM

Inventors

• Walters Craig R
• Bamdhamravuri Ram Sai Manoj
• Berger Deanna Postles Dunn
• Ditomaso Dominic
• Buyuktosunoglu Alper

Classifications

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/084 Primary

  with a shared cache · CPC title

• G06F13/1663 Primary

  Access to shared memory · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title