Concurrent modification of shared cache line by multiple processors

Patent metadata

Field	Value
Publication number	US-10769068-B2
Application number	US-201715809049-A
Country	US
Kind code	B2
Filing date	Nov 10, 2017
Priority date	Nov 10, 2017
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.

First claim

What is claimed is:

1. A computer program product for facilitating processing within a computing environment, the computer program product comprising:
at least one computer readable storage medium readable by at least one processing circuit and storing instructions for performing a method comprising:
obtaining, from a plurality of processors of the computing environment, a plurality of store requests to store to a shared cache line, the plurality of store requests being of a concurrent store type in which non-exclusive access to the shared cache line for storing data by the plurality of processors is being requested; and
storing concurrently, based on the plurality of store requests, data to the shared cache line, wherein the plurality of processors concurrently maintain write access to the shared cache line, and wherein the storing concurrently comprises storing the data directly to the shared cache line absent storing the data in one or more private caches of the plurality of processors and absent inspection by the plurality of processors of content within the shared cache line being updated by the data.

2. The computer program product of claim 1 , wherein the method further comprises setting a cache directory state associated with the shared cache line to shared-modifiable indicating multiple store requests by multiple processors are permissible.

3. The computer program product of claim 1 , wherein the data comprises an update to a global shared-modifiable structure maintained in the shared cache line.

4. The computer program product of claim 1 , wherein the storing concurrently the data is performed absent sending a cross-invalidate to the plurality of processors.

5. The computer program product of claim 1 , wherein the method further comprises:
obtaining a fetch request requesting access to the shared cache line, the fetch request being different from the concurrent store type;
performing serialization for the shared cache line based on the fetch request; and
reading the data from the shared cache line, based on completing the serialization.

6. The computer program product of claim 5 , wherein the performing serialization comprises:
stopping outstanding stores to the shared cache line; and
synchronizing data of the shared cache line.

7. The computer program product of claim 5 , wherein the method further comprises changing ownership state of the shared cache line, based on the fetch request, from shared-modifiable to another state.

8. The computer program product of claim 7 , wherein the other state is exclusive or read-only, based on the fetch request.

9. The computer program product of claim 1 , wherein the obtaining the plurality of store requests comprises receiving a plurality of fetch due to non-coherent store requests from the plurality of processors, the plurality of fetch due to non-coherent store requests being architecturally defined to allow non-blocking modifications to the shared cache line.

10. The computer program product of claim 1 , wherein the storing concurrently the data to the shared cache line comprises updating a shared counter of the shared cache line without knowing a value of the shared counter at a time of the storing.

11. A computer system for facilitating processing within a computing environment, the computer system comprising:
a memory; and
at least one processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
obtaining, from a plurality of processors of the computing environment, a plurality of store requests to store to a shared cache line, the plurality of store requests being of a concurrent store type in which non-exclusive access to the shared cache line for storing data by the plurality of processors is being requested; and
storing concurrently, based on the plurality of store requests, data to the shared cache line, wherein the plurality of processors concurrently maintain write access to the shared cache line, and wherein the storing concurrently comprises storing the data directly to the shared cache line absent storing the data in one or more private caches of the plurality of processors and absent inspection by the plurality of processors of content within the shared cache line being updated by the data.

12. The computer system of claim 11 , wherein the method further comprises setting a cache directory state associated with the shared cache line to shared-modifiable indicating multiple store requests by multiple processors are permissible.

13. The computer system of claim 11 , wherein the method further comprises:
obtaining a fetch request requesting access to the shared cache line, the fetch request being different from the concurrent store type;
performing serialization for the shared cache line based on the fetch request; and
reading the data from the shared cache line, based on completing the serialization.

14. The computer system of claim 11 , wherein the obtaining the plurality of store requests comprises receiving a plurality of fetch due to non-coherent store requests from the plurality of processors, the plurality of fetch due to non-coherent store requests being architecturally defined to allow non-blocking modifications to the shared cache line.

15. The computer system of claim 11 , wherein the storing concurrently the data to the shared cache line comprises updating a shared counter of the shared cache line without knowing a value of the shared counter at a time of the storing.

16. A computer-implemented method of facilitating processing within a computing environment, the computer-implemented method comprising:
obtaining, from a plurality of processors of the computing environment, a plurality of store requests to store to a shared cache line, the plurality of store requests being of a concurrent store type in which non-exclusive access to the shared cache line for storing data by the plurality of processors is being requested; and
storing concurrently, based on the plurality of store requests, data to the shared cache line, wherein the plurality of processors concurrently maintain write access to the shared cache line, and wherein the storing concurrently comprises storing the data directly to the shared cache line absent storing the data in one or more private caches of the plurality of processors and absent inspection by the plurality of processors of content within the shared cache line being updated by the data.

17. The computer-implemented method of claim 16 , further comprising setting a cache directory state associated with the shared cache line to shared-modifiable indicating multiple store requests by multiple processors are permissible.

18. The computer-implemented method of claim 16 , further comprising:
obtaining a fetch request requesting access to the shared cache line, the fetch request being different from the concurrent store type;
performing serialization for the shared cache line based on the fetch request; and
reading the data from the shared cache line, based on completing the serialization.

19. The computer-implemented method of claim 16 , wherein the obtaining the plurality of store requests comprises receiving a plurality of fetch due to non-coherent store requests from the plurality of processors, the plurality of fetch due to non-coherent store requests being architecturally defined to allow non-blocking modifications to the shared cache line.

20. The computer-implemented method of claim 16 , wherein the storing concurrently the data to

Assignees

• IBM

Inventors

• Matsakis Nicholas C
• Walters Craig R
• Bartik Jane H
• Shum Chung-Lung K
• Tzortzatos Elpida

Classifications

• G06F12/0817 Primary

  using directory methods · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/084 Primary

  with a shared cache · CPC title

• G06F12/0828 Primary

  with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions · CPC title