Lateral persistence directory states

Patent metadata

Field	Value
Publication number	US-2023054424-A1
Application number	US-202117407248-A
Country	US
Kind code	A1
Filing date	Aug 20, 2021
Priority date	Aug 20, 2021
Publication date	Feb 23, 2023
Grant date	—

Abstract

Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

First claim

What is claimed is:

1 . A computer-implemented method comprising:
defining one or more processor units having a plurality of caches, wherein each processor unit comprises a processor having at least one cache from the plurality of caches, and wherein each of the one or more processor units are coupled together by an interconnect fabric; for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class in the one or more congruence classes comprises a chronology vector; arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains; determining a first cache line to evict based on the chronology vector for the first cache line; and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

2 . The computer-implemented method of claim 1 , further comprising writing the first cache line to the target cache and incrementing the lateral persistence tag bits for the first cache line.

3 . The computer-implemented method of claim 2 , wherein writing the first cache line to the target cache comprises:
selecting a second cache line to evict from the target cache; determining a second scope for the second cache line; and determining an eviction location for the second cache line based on the second scope, wherein the eviction location comprises at least one of a lateral cache and a main memory.

4 . The computer-implemented method of claim 2 , wherein writing the first cache line to the target cache comprises:
determining a cache replacement policy comprising one or more cache install positions; determining a scope for the first cache line for the target cache, wherein the scope determines an originator of a request to install the first cache line, and wherein the originator comprises at least one of a processor local to the target cache and a lateral cache; and determining an install position of the first cache line based on a percentage of cache lines installed by the processor local to the target cache and a percentage of cache lines installed by lateral caches.

5 . The computer-implemented method of claim 4 , wherein the one or more cache install positions comprise most recently used (MRU) position, middle least recently used (mid-LRU) position, and least recently used (LRU) position.

6 . The computer-implemented method of claim 1 , wherein determining the target cache for installing the first cache line comprises:
determining a target cluster of caches based on the scope of the first cache line; and selecting the target cache from the target cluster of caches.

7 . The computer-implemented method of claim 6 , wherein determining the target cluster of caches based on the scope of the first cache line and a saturation metric associated with the target cache comprises:
determining a scope domain for each cluster of caches; and selecting the target cluster of caches based on a scope domain for the target cluster being higher than the scope of the first cache line.

8 . The computer-implemented method of claim 6 , wherein determining the target cluster of caches based on the scope of the first cache line and a saturation metric associated with the target cache comprises:
analyzing a combined saturation metric for each cluster of caches, wherein the combined saturation metric comprises the saturation metric combined for each cache in a cluster of caches; and selecting the target cluster of caches based on the combined saturation metric for the target cluster being a lowest combined saturation metric among each cluster of caches.

9 . The computer-implemented method of claim 6 , wherein selecting the target cache from the target cluster of caches comprises:
analyzing a saturation metric of each cache in the target cluster of caches; selecting the target cache based on the saturation metric for the target cache being a lowest saturation metric among each cache in the target cluster of caches.

10 . The computer-implemented method of claim 1 , wherein the saturation metric comprises at least one of a number of installs defined by processor misses and a number of installs in a cache from lateral caches.

11 . A system comprising:
one or more processor units having a plurality of caches, wherein each processor unit comprises a processor having at least one cache from the plurality of caches, and wherein each of the one or more processor units are coupled together by an interconnect fabric, and a cache controller configured to perform:
for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class in the one or more congruence classes comprises a chronology vector;
arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains;
determining a first cache line to evict based on the chronology vector for the cache line; and
determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

12 . The system of claim 11 , wherein the cache controller is further configured to perform writing the first cache line to the target cache and incrementing the first lateral persistence bit tags for the first cache line.

13 . The system of claim 12 , wherein writing the first cache line to the target cache comprises:
selecting a second cache line to evict from the target cache; determining a second scope for the second cache line; and determining an eviction location for the second cache line based on the second scope, wherein the eviction location comprises at least one of a lateral cache and a main memory.

14 . The system of claim 12 , wherein writing the first cache line to the target cache comprises:
determining a cache replacement policy comprising one or more cache install positions; determining an originator of a request to install the first cache line to the target cache, wherein the originator comprises at least one of a processor local to the target cache and a lateral cache; and determining an install position of the first cache line based on a percentage of cache lines installed by the processor local to the target cache and a percentage of cache lines installed by lateral caches.

15 . The system of claim 11 , wherein determining the target cache for installing the first cache line comprises:
determining a target cluster of caches based on the scope of the first cache line; and selecting the target cache from the target cluster of caches.

16 . A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:
defining one or more processor units having a plurality of caches, wherein each processor unit comprises a processor having at least one cache from the plurality of caches, and wherein each of the one or more processor units are coupled together by an interconnect fabric; for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class in the one or more congruence classes comprises

Assignees

• IBM

Inventors

• Bamdhamravuri Ram Sai Manoj
• Walters Craig R
• Jacobi Christian
• Bronson Timothy
• Alexander Gregory William
• Huynh Hieu T
• Sonnelitter Iii Robert J
• Kohl Jason D
• Berger Deanna P D
• Branciforte Richard Joseph

Classifications

• G06F12/123 Primary

  with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list · CPC title

• G06F2212/6046

  Using a specific cache allocation policy other than replacement policy · CPC title

• G06F12/126

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• G06F12/0891 Primary

  using clearing, invalidating or resetting means · CPC title