Efficient generation of instrumentation data for direct memory access operations

Patent metadata

Field	Value
Publication number	US-2021216430-A1
Application number	US-202016738311-A
Country	US
Kind code	A1
Filing date	Jan 9, 2020
Priority date	Jan 9, 2020
Publication date	Jul 15, 2021
Grant date	—

Abstract

Aspects of the invention include efficient generation of instrumentation data for direct memory access operations. A non-limiting example apparatus includes an instrumentation component, residing in a cache in communication with a plurality of processing units, an accelerator, and a plurality of input output interfaces. The cache includes a direct memory access monitor that receives events from the accelerator its respective I/O interface and stores DMA state and latency for each event. The cache also includes a bucket including a DMA counter and a latency counter in communication with the DMA monitor, wherein the bucket stores in the DMA counter a count of DMAs coming from a source and stores in the latency counter the latency measured for each DMA coming from the source.

First claim

1 . A system comprising:
a central processor comprising:
a level three (L3) cache in communication with a plurality of processing units;
an accelerator; and
a plurality of input output (I/O) interfaces,
wherein the L3 cache comprises a direct memory access (DMA) monitor that receives events from the accelerator and the plurality of I/O interfaces and stores DMA state and latency for each event, and the DMA monitor comprises a bucket that includes a DMA counter and a latency counter, wherein the bucket stores in the DMA counter a count of DMAs coming from a source and stores in the latency counter the latency measured for each DMA coming from the source.

2 . The system of claim 1 , further comprising a total DMA fetch counter in communication with the DMA monitor.

3 . The system of claim 1 , further comprising a total DMA store counter in communication with the DMA monitor.

4 . The system of claim 1 , further comprising a resource unavailability counter in communication with the DMA monitor.

5 . The system of claim 1 , further comprising a threshold detector.

6 . The system of claim 5 , wherein the threshold detector triggers events based on a total DMA fetch counter.

7 . The system of claim 5 , wherein the threshold detector triggers events based on a total DMA store counter.

8 . The system of claim 5 , wherein the threshold detector triggers events based on a resource unavailability counter.

9 . The system of claim 1 , further comprising a global period timer.

10 . The system of claim 1 , wherein the bucket represents a type of a DMA.

11 . The system of claim 1 , wherein events are generated by the accelerator.

12 . The system of claim 1 , wherein events are generated by one of the plurality of I/O interfaces.

13 . A method of monitoring direct memory access (DMA), comprising:
receiving, at a direct memory access monitor (DMA) monitor in a level three (L3) cache, events from an accelerator and a plurality of input/output (I/O) interfaces, the L3 cache in communication with and located on the same central processor as an accelerator and the I/O interfaces; and storing a DMA state and latency for each event, wherein the DMA monitor comprises a bucket including a DMA counter and a latency counter and the bucket stores in the DMA counter a count of DMAs coming from a source and stores in the latency counter the latency measured for each DMA coming from the source, the source one of an I/O interface of the plurality of I/O interfaces and the accelerator.

14 . (canceled)

15 . (canceled)

16 . The method of claim 13 , further comprising updating a hit state with a hit state of the DMA.

17 . The method of claim 13 , further comprising monitoring resource availability.

18 . The method of claim 13 , further comprising monitoring non-tracked DMA to provide statistics on the non-tracked DMA.

19 . The method of claim 13 , further comprising checkstopping when a latency threshold is exceeded.

20 . (canceled)

Assignees

• IBM

Inventors

• Klein Matthias
• Berger Deanna P D
• Walters Craig R

Classifications

• G06F2201/88

  Monitoring involving counting · CPC title

• G06F11/349 Primary

  for interfaces, buses · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F2213/28

  DMA · CPC title