Controller address contention assumption

Patent metadata

Field	Value
Publication number	US-2021034438-A1
Application number	US-201916527424-A
Country	US
Kind code	A1
Filing date	Jul 31, 2019
Priority date	Jul 31, 2019
Publication date	Feb 4, 2021
Grant date	—

Abstract

Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.

First claim

What is claimed is:

1 . A computer-implemented method comprising:
receiving, by a shared controller, a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller; performing, by the shared controller, an address compare using a memory address of the data; in response to the memory address matching a memory address stored in the shared controller, acknowledging, by the shared controller, the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets; and in response to release of the data by a second requesting agent, transmitting, by the shared controller, the data to the first requesting agent.

2 . The computer-implemented method of claim 1 , wherein the acknowledging comprises:
exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least one intermediary controller transmits an identity of the first requesting agent and a type of operation associated with the requested data, and wherein the shared controller transmits an acceptance.

3 . The computer-implemented method of claim 2 , the at least one intermediary controller including a plurality of intermediary controllers, wherein the exchange of information further comprises a priority of an operation, and wherein the shared controller transmits the released data to a respective requesting agent of each intermediary controller of the plurality of intermediary controllers based on the respective priority.

4 . The computer-implemented method of claim 2 further comprising:
storing, by the shared controller, the identity of the requesting agent and the type of operation in a queue.

5 . The computer-implemented method of claim 1 , the at least one intermediary controller including a plurality of intermediary controllers that each have a fetch request for a read-only operation of the data, wherein the shared controller transmits the released data to the respective requesting agents of the plurality of intermediary controllers in parallel.

6 . The computer-implemented method of claim 1 , the at least one intermediary controller including a plurality of intermediary controllers that each have a fetch request for a respective write operation of the data, wherein the shared controller sequentially transmits the released data to a respective requesting agent of each intermediary controller of the plurality of intermediary controllers based on a time of each fetch request.

7 . The computer-implemented method of claim 1 , the at least one intermediary controller including a plurality of intermediary controllers, wherein a first subset of the plurality of intermediary controllers each have a fetch request for a respective write operation of the data, wherein a second subset of the plurality of intermediary controllers each have a fetch request for a respective read-only operation of the data, the shared controller estimating a time of completion of the read-only operation being shorter than the write operation and transmitting the released data for requesting agents associated with second subset prior to requesting agents associated with the first subset.

8 . A system comprising:
a memory having computer readable instructions; and one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
receiving, by a shared controller, a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller;
performing, by the shared controller, an address compare using a memory address of the data;
in response to the memory address matching a memory address stored in the shared controller, acknowledging, by the shared controller, the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets; and
in response to release of the data by a second requesting agent, transmitting, by the shared controller, the data to the first requesting agent.

9 . The system of claim 8 , wherein the acknowledging comprises:
exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least one intermediary controller transmits an identity of the first requesting agent and a type of operation associated with the requested data, and wherein the shared controller transmits an acceptance.

10 . The system of claim 9 , the at least one intermediary controller including a plurality of intermediary controllers, wherein the exchange of information further comprises a priority of an operation, and wherein the shared controller transmits the data to a respective requesting agent of each intermediary controller of the plurality of intermediary controllers based on the respective priority.

11 . The system of claim 9 further comprising:
storing, by the shared controller, the identity of the first requesting agent and the type of operation in a queue.

12 . The system of claim 8 , the at least one intermediary controller including a plurality of intermediary controllers that each have a fetch request for a read-only operation of the data, wherein the shared controller transmits the released data to the respective requesting agents of the plurality of intermediary controllers in parallel.

13 . The system of claim 8 , the at least one intermediary controller including a plurality of intermediary controllers that each have a fetch request for a respective write operation of the data, wherein the shared controller sequentially transmits the released data to a respective requesting agent of each intermediary controller of the plurality of intermediary controllers based on a time of each fetch request.

14 . The system of claim 8 , the at least one intermediary controller including a plurality of intermediary controllers, wherein a first subset of the plurality of intermediary controllers each have a fetch request for a respective write operation of the data, wherein a second subset of the plurality of intermediary controllers each have a fetch request for a respective read-only operation of the data, the shared controller estimating a time of completion of the read-only operation being shorter than the write operation and transmitting the released data to requesting agents associated with second subset prior to requesting agents associated with the first subset.

15 . A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
receiving, by a shared controller, a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller; performing, by the shared controller, an address compare using a memory address of the data; in response to the memory address matching a memory address stored in the shared controller, acknowledging, by the shared controller, the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets; and in response to release of the data by a second requesting agent, transmitting, by the shared controller, the data to the first requesting agent.

16 . The computer program product of claim 15 , wherein the acknowledging comprises:
exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least

Assignees

• IBM

Inventors

• Sonnelitter Iii Robert J
• Fee Michael
• Walters Craig R
• O'Neill Arthur
• Klein Matthias

Classifications

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F9/528 Primary

  by using speculative mechanisms · CPC title

• G06F9/3802

  Instruction prefetching · CPC title