Memory state indicator

Patent metadata

Field	Value
Publication number	US-10635307-B2
Application number	US-201514755747-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	Jun 30, 2015
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

Aspects include a computer-implemented method includes receiving an instruction at a processor, the instruction associated with a memory block having an address, and accessing a state indicator by the processor. The state indicator indicates whether the memory block is in a pre-defined state, and the state indicator is accessible by the processor independent of the memory block. The method also includes, based on the state indicator indicating that the memory block is in the pre-defined state, inspecting a subset of data values in the memory block, and identifying the pre-defined state of the memory block based on the subset of data values.

First claim

What is claimed is:

1. A system comprising:
a memory having computer readable instructions; and
one or more processing devices for executing the computer readable instructions, the computer readable instructions comprising:
receiving an instruction at a processor, the instruction associated with a memory block having an address, the memory block configured to store data therein;
accessing a state indicator by the processor, the state indicator indicating whether the memory block is in one of a plurality of predefined states, each of the plurality of pre-defined states associated with a pattern of data values, the state indicator accessible by the processor independent of the memory block;
based on the state indicator indicating that the memory block is in one of the plurality of predefined states, inspecting only an initial portion of data values in the memory block to detect the pattern of data values, wherein the initial portion does not include all of the data values in the memory block;
identifying which of the plurality of pre-defined states that the memory block is in, wherein identifying is based on the detected pattern of data values and based on an assumption that the detected pattern is repeated across all lines of the memory block;
determining that the identified pre-defined state is not associated with one or more redundant operations; and
executing the instruction associated with the memory block in response to the determination that the pre-defined state is not associated with the one or more redundant operations.

2. The system of claim 1 , wherein the pre-defined state is identified based on the detected pattern of data values without inspecting any other portion of the memory block.

3. The system of claim 1 , wherein identifying which of the particular state of the plurality of pre-defined states includes comparing the detected pattern of data values to stored patterns associated with corresponding known states.

4. The system of claim 1 , wherein accessing the state indicator includes determining based on the state indicator whether the memory block is in one of the plurality of predefined states, and determining includes at least one of preventing and eliminating the need for operations on the contents of the memory block to be completed.

5. The system of claim 1 , wherein the state indicator is stored in a data structure, the data structure selected from at least one of metadata associated with the memory block, a configuration table, a status table and an addressing table.

6. The system of claim 1 , wherein the instruction is an instruction to move data from a source memory block to a destination memory block, the method further comprising:
accessing a first state indicator associated with the source memory block, determining based on the first state indicator whether the source memory block is in one of the plurality of pre-defined states, and based on the first state indicator indicating that the source memory block is in one of the plurality of pre-defined states, identifying a first state of the plurality of pre-defined states of the source memory block by only inspecting a subset of the source memory block, wherein the subset of the source memory block does not include all of the data values in the source memory block;
accessing a second state indicator associated with the destination memory block, determining based on the second state indicator whether the destination memory block is in one of the plurality of pre-defined states, and based on the second state indicator indicating that the destination memory block is in one of the plurality of pre-defined states, identifying a second state of the plurality of pre-defined states of the destination memory block by only inspecting a subset of the destination memory block, wherein the subset of the destination memory block does not include all of the data values in the destination memory block;
comparing the first state to the second state; and
based on the first state matching the second state, executing the instruction without copying redundant data between the source memory block and the destination memory block.

7. The system of claim 1 , wherein the instruction is an instruction to initialize the memory block to an initialization state, the method further comprising:
comparing the detected pattern to a stored pattern associated with the initialization state;
based on the detected pattern matching the stored pattern, executing the instruction without altering the memory block; and
based on the detected pattern not matching the stored pattern, setting the memory block to the initialization state.

8. The system of claim 1 , wherein the detected pattern is a repeated pattern.

9. The system of claim 8 , wherein the repeated pattern is a binary pattern or a data word.

10. The system of claim 8 , wherein the repeated pattern is repeatedly sequentially.

11. The system of claim 1 , wherein the redundant operations includes at least one of: copying operations, re-initializations, and overwrites.

12. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processing device to cause the processing device to perform a method comprising:
receiving an instruction at a processor, the instruction associated with a memory block having an address, the memory block configured to store data therein;
accessing a state indicator by the processor, the state indicator indicating whether the memory block is in one of a plurality of predefined states, each of the plurality of predefined states associated with a respective pattern of data values, the state indicator accessible by the processor independent of the memory block;
based on the state indicator indicating that the memory block is in one of the plurality of predefined states, inspecting only an initial portion of data values in the memory block to detect the pattern of data values, wherein the initial portion does not include all of the data values in the memory block;
identifying which of the plurality of pre-defined states that the memory block is in, wherein identifying is based on the detected pattern of data values and based on an assumption that the detected pattern is repeated across all lines of the memory block;
determining that the identified pre-defined state is not associated with one or more redundant operations; and
executing the instruction associated with the memory block in response to the determination that the pre-defined state is not associated with the one or more redundant operations.

13. The computer program product of claim 12 , wherein identifying includes identifying which of the plurality of pre-defined states the memory block is in based on the initial portion without inspecting any other portion of the memory block.

14. The computer program product of claim 12 , wherein identifying which of the plurality of pre-defined states the memory block is in includes comparing the detected pattern of data values to stored patterns associated with corresponding known states.

15. The computer program product of claim 12 , wherein the state indicator is stored in a data structure, the data structure selected from at least one of metadata associated with the memory block, a configuration table, a status table and an addressing table.

16. The computer program product of claim 12 , wherein accessing the state indicator includes determining based on the state indicator whether the memory block is in one of the plurality of predefined states, and determining in

Assignees

• IBM

Inventors

• Bartik Jane H
• Sutton Peter G
• Walters Craig R
• Webb Charles F

Classifications

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0673 Primary

  Single storage device · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0617

  in relation to availability · CPC title