Remote Cache Invalidation
US-2026056885-A1 · Feb 26, 2026 · US
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Vash James patents
Vash James is listed as an inventor on 53 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Vash James |
| Total patents | 53 |
| First publication | Jun 16, 2015 |
| Latest publication | Feb 26, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Multiple independent on-chip interconnect
US-12561267-B2 · Feb 24, 2026 · US
Scalable System on a Chip
US-2026044451-A1 · Feb 12, 2026 · US
Invalidation of Permission Information Stored by Another Processor
US-2026017217-A1 · Jan 15, 2026 · US
Remote cache invalidation
US-12487927-B2 · Dec 2, 2025 · US
Invalidation of permission information stored by another processor
US-12468644-B2 · Nov 11, 2025 · US
DSB Operation with Excluded Region
US-2025278274-A1 · Sep 4, 2025 · US
Scalable Cache Coherency Protocol
US-2025278366-A1 · Sep 4, 2025 · US
Scalable system on a chip
US-12399830-B2 · Aug 26, 2025 · US
Invalidation of Permission Information Stored by Another Processor
US-2025245179-A1 · Jul 31, 2025 · US
Recent patents
Latest publications not already listed above.
Scalable cache coherency protocol
US-12332792-B2 · Jun 17, 2025 · US
DSB operation with excluded region
US-12321746-B2 · Jun 3, 2025 · US
Mechanisms to utilize communication fabric via multi-port architecture
US-12277074-B1 · Apr 15, 2025 · US
Remote Cache Invalidation
US-2025103492-A1 · Mar 27, 2025 · US
Memory error tracking and logging
US-12253913-B2 · Mar 18, 2025 · US
Memory Error Tracking and Logging
US-2024427663-A1 · Dec 26, 2024 · US
Scalable System on a Chip
US-2024411695-A1 · Dec 12, 2024 · US
Scalable System on a Chip
US-2024370371-A1 · Nov 7, 2024 · US
Scalable Cache Coherency Protocol
US-2024273024-A1 · Aug 15, 2024 · US
Scalable system on a chip
US-12007895-B2 · Jun 11, 2024 · US
Scalable cache coherency protocol
US-11947457-B2 · Apr 2, 2024 · US
Memory error tracking and logging
US-11934265-B2 · Mar 19, 2024 · US
Scalable system on a chip
US-11934313-B2 · Mar 19, 2024 · US
Scalable cache coherency protocol
US-11868258-B2 · Jan 9, 2024 · US
Multiple Independent On-chip Interconnect
US-2023350828-A1 · Nov 2, 2023 · US
Scalable system on a chip
US-11803471-B2 · Oct 31, 2023 · US
DSB Operation with Excluded Region
US-2023333851-A1 · Oct 19, 2023 · US
Memory Error Tracking and Logging
US-2023305924-A1 · Sep 28, 2023 · US
Coprocessor context priority
US-11768690-B2 · Sep 26, 2023 · US
DSB operation with excluded region
US-11720360-B2 · Aug 8, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Apple Inc | 48 |
| Intel Corp | 5 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0831 | 28 |
| G06F2212/1024 | 26 |
| G06F12/0824 | 24 |
| G06F12/0815 | 24 |
| G06F12/0833 | 20 |