Remote cache invalidation

Patent metadata

Field	Value
Publication number	US-12487927-B2
Application number	US-202418582305-A
Country	US
Kind code	B2
Filing date	Feb 20, 2024
Priority date	Sep 25, 2023
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

First claim

What is claimed is:

1 . An apparatus, comprising:
coprocessor circuitry that includes:
coprocessor cache circuitry; and
cache invalidation control circuitry;
primary processor circuitry that includes:
an execution pipeline; and
primary processor cache circuitry;
wherein:
the primary processor circuitry is configured to:
map memory pages for the coprocessor circuitry;
unmap a page that was mapped for the coprocessor circuitry; and
based on the unmap and execution of a remote invalidate instruction by the execution pipeline, send a cache invalidate command to the coprocessor circuitry; and

the cache invalidation control circuitry is configured to, in response to the cache invalidate command, invalidate one or more cache lines in the coprocessor cache circuitry, where the cache invalidation control circuitry is configured to perform the invalidation without executing any instructions on the coprocessor circuitry.

2 . The apparatus of claim 1 , further comprising:
coherence control circuitry; and other processor circuitry that includes other cache circuitry; wherein:
the coherence control circuitry is configured to maintain coherence between the other cache circuitry and the primary processor cache circuitry, including to, based on the unmap, invalidate one or more cache lines of the other cache circuitry to maintain coherence; and
the coherence control circuitry is not configured to maintain coherence, for the unmap, between the primary processor cache circuitry and the coprocessor cache circuitry.

3 . The apparatus of claim 1 , wherein:
the coprocessor circuitry further includes translation lookaside buffer circuitry that implements entries configured to store translations from a first address space to a second address space; and the primary processor circuitry is further configured to, based on the unmap, send a translation lookaside buffer invalidate command to the coprocessor circuitry that invalidates one or more corresponding entries in the translation lookaside buffer circuitry.

4 . The apparatus of claim 3 , wherein:
the primary processor circuitry is further configured to send:
a first barrier command between the translation lookaside buffer invalidate command and the cache invalidate command; and
a second barrier command after the cache invalidate command.

5 . The apparatus of claim 4 , wherein:
the coprocessor circuitry is further configured to respond to the cache invalidate command before an eviction for an address that matches the cache invalidate command is complete; and the second barrier command ensures completion of the eviction.

6 . The apparatus of claim 1 , wherein:
the coprocessor circuitry supports instructions with virtual addresses and is configured to translate virtual addresses to physical addresses; the coprocessor cache circuitry is tagged using physical addresses; and the cache invalidate command indicates a physical address to be invalidated.

7 . The apparatus of claim 1 , wherein:
the invalidation of the one or more cache lines in the coprocessor cache circuitry includes invalidation of multiple cache lines in the coprocessor cache circuitry based on a single cache invalidate command that indicates to invalidate multiple cache lines of the coprocessor cache circuitry.

8 . The apparatus of claim 1 , wherein:
the apparatus supports multiple shareability domains; the primary processor circuitry includes one or more caches that are included in one or more of the multiple shareability domains, including the primary processor cache circuitry; and the coprocessor cache circuitry is not included in any shareability domain in which any cache of the primary processor circuitry is included.

9 . The apparatus of claim 1 , wherein:
the cache invalidate command is included in a packet transmitted on a communication fabric, wherein the packet includes at least the following:
information that specifies one or more addresses to invalidate; and
an identifier of the coprocessor circuitry.

10 . The apparatus of claim 1 , wherein:
the coprocessor circuitry further comprises:
lower-level cache circuitry, where the lower-level cache circuitry is closer to an execution pipeline of the coprocessor circuitry than the coprocessor cache circuitry in a cache hierarchy; and
coprocessor cache coherence circuitry; and
the coprocessor cache coherence circuitry is configured to, in response to the invalidation at the coprocessor cache circuitry, invalidate one or more corresponding cache lines in the lower-level cache circuitry.

11 . The apparatus of claim 1 , wherein the apparatus is a computing device that further includes:
a display; and network interface circuitry.

12 . A method, comprising:
mapping, by a processor, memory pages for a coprocessor; unmapping, by the processor, a page that was mapped for the coprocessor; sending, by the processor based on the unmapping and execution of a remote invalidate instruction, a cache invalidate command to coprocessor; and invalidating, by the coprocessor in response to the cache invalidate command, one or more cache lines of coprocessor cache, wherein the invalidating is performed without executing any instructions on the coprocessor.

13 . The method of claim 12 , further comprising:
storing, implementing, by the coprocessor, by a translation lookaside buffer of the coprocessor, translations from a first address space to a second address space; and sending, by the coprocessor based on the unmap, a translation lookaside buffer invalidate command that invalidates one or more corresponding entries in the translation lookaside buffer.

14 . The method of claim 13 , further comprising:
sending, by the processor to the coprocessor:
a first barrier command between the translation lookaside buffer invalidate command and the cache invalidate command; and
a second barrier command after the cache invalidate command.

15 . A non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware circuit that includes:
coprocessor circuitry that includes:
coprocessor cache circuitry; and
cache invalidation control circuitry;
primary processor circuitry that includes:
an execution pipeline; and
primary processor cache circuitry;
wherein:
the primary processor circuitry is configured to:
map memory pages for the coprocessor circuitry;
unmap a page that was mapped for the coprocessor circuitry; and
based on the unmap and execution of a remote invalidate instruction by the execution pipeline, send a cache invalidate command to the coprocessor circuitry; and

the cache invalidation control circuitry is configured to, in response to the cache invalidate command, invalidate one or more cache lines in the coprocessor cache circuitry, where the cache invalidation control circuitry is configured to perform the invalidation without executing any instructions on the coprocessor circuitry.

16 . The non-transitory computer-readable medium of claim 15 , wherein the hardware circuit further includes:
coherence control circuitry; and other processor circuitry that includes other cache circuitry; wherein:
the coherence control circuitry is configured to maintain coherence between the other cache circuitry and the primary processor cache circuitry, including to, based on the unmap, invalidate one or more cache lines of the other cache cir

Assignees

• Apple Inc

Inventors

• Feero Brett S
• Bradford Dennis R
• Garg Gaurav
• Gonion Jeff
• Semeria Bernard J
• Vash James
• Russo Richard F

Classifications

• G06F12/0882

  Page mode · CPC title

• G06F12/1045

  associated with a data cache · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F2212/682

  Multiprocessor TLB consistency · CPC title

• G06F12/0857

  by multiple requestors · CPC title