Scalable cache coherency protocol

Patent metadata

Field	Value
Publication number	US-11868258-B2
Application number	US-202318160575-A
Country	US
Kind code	B2
Filing date	Jan 27, 2023
Priority date	Sep 11, 2020
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

First claim

What is claimed is:

1. A system comprising:
a plurality of coherent agent circuits, wherein a given agent circuit of the plurality of coherent agent circuits comprises one or more caches to cache memory data; and
a directory configured to track at least: (i) which of the plurality of coherent agent circuits is caching copies of a plurality of cache blocks in a memory in the system, and (ii) states of the cached copies in the plurality of coherent agent circuits;
a coherency controller circuit coupled to the directory, wherein based on a first request for a first cache block by a first agent circuit of the plurality of coherent agent circuits, the coherency controller circuit is configured to:
read an entry corresponding to the first cache block from the directory, and
issue a message to a second agent circuit of the plurality of coherent agent circuits that has a cached copy of the first cache block according to the entry, wherein the message requests a state change in the state of the cached copy in the second agent circuit, and
include an identifier of a first state of the first cache block in the second agent circuit in the message; and

wherein, based on the message, the second agent circuit is configured to:
compare the first state to a second state of the first cache block in the second agent circuit, and
delay processing of the state change based on the first state not matching the second state until the second state is changed to the first state.

2. The system as recited in claim 1 wherein the second agent circuit is configured to change the second state to the first state in response to a different message related to a different request than the first request.

3. The system as recited in claim 1 ,
wherein the coherency controller circuit is configured to:
determine a completion count indicating a number of completions that the first agent circuit will receive for the first request, wherein the determination is based on the states from the entry,
include the completion count in a plurality of messages issued based on the first request including the message issued to the second agent circuit; and

wherein the first agent circuit is configured to:
initialize a completion counter with the completion count based on receiving an initial completion from one of the plurality of coherent agent circuits,
update the completion counter based on receiving a subsequent completion from another one of the plurality of coherent agent circuits, and
complete first request based on the completion counter.

4. The system as recited in claim 3 wherein the coherency controller circuit is configured to update the states in the entry of the directory to reflect completion of the first request based on issuing the plurality of messages.

5. The system as recited in claim 1 wherein:
the first agent circuit is configured to detect a second message received by the first agent circuit to the first cache block,
the second message requests another state change to the first cache block, and
the first agent circuit is configured to absorb the second message into the first request.

6. The system as recited in claim 5 wherein the first agent circuit is configured to process the second message subsequent to completing the first request.

7. The system as recited in claim 6 wherein the first agent circuit is configured to forward the first cache block to a third agent circuit indicated in the second message subsequent to completing the first request.

8. The system as recited in claim 1 wherein:
a third agent circuit is configured to generate a conditional change to exclusive state request based on a store conditional instruction to a second cache block that is in a valid state at the third agent circuit, and
the coherency controller circuit is configured to determine if the third agent circuit retains a valid copy of the second cache block based on a second entry in the directory associated with the second cache block,
the coherency controller circuit is configured to transmit a completion indicating failure to the third agent circuit based on a determination that the third agent circuit no longer retains the valid copy of the second cache block, and
the coherency controller circuit is configured to terminate the conditional change to exclusive request based on the determination that the third agent circuit no longer retains the valid copy of the second cache block.

9. The system as recited in claim 8 wherein the coherency controller circuit is configured to issue one or more messages to other ones of the plurality of coherent agent circuits as indicated by the second entry based on a determination that the third agent circuit retains the valid copy of the second cache block, wherein the one or more messages request respective state changes in the plurality of coherent agent circuits from the second cache block.

10. The system as recited in claim 1 wherein the message indicates that the second agent circuit is to transmit the first cache block to the first agent circuit based on the first state being primary shared, and wherein the message indicates that the second agent circuit is not to transmit the first cache block based on the first state being secondary shared.

11. The system as recited in claim 1 wherein the message indicates that the second agent circuit is to transmit the first cache block to the first agent circuit based on the first state being primary shared, and wherein the message indicates that the second agent circuit is to transmit the first cache block even in the event that the first state is secondary shared.

12. A coherent agent circuit comprising:
one or more caches to cache memory data; and
a control circuit coupled to the one or more caches, wherein:
the control circuit is configured to receive a message from a coherency controller circuit when the one or more caches has a cached copy of a first cache block that has been requested by a different coherent agent circuit,
the message requests a state change in the state of the cached copy in the one or more caches,
the message includes an identifier of a first state in the one or more caches according to a directory in the coherency controller circuit,
the control circuit is configured to compare the first state of the first cache block to a second state of the first cache block in the one or more caches, and
the control circuit is configured to delay processing of the message based on the first state not matching the second state until the second state is changed to the first state.

13. The coherent agent circuit as recited in claim 12 wherein the control circuit is configured to change the second state to the first state in response to a different message from the coherency controller circuit.

14. The coherent agent circuit as recited in claim 12 wherein the message indicates that the coherent agent circuit is to transmit the first cache block to the different coherent agent circuit based on the first state being primary shared, and wherein the message indicates that the coherent agent circuit is not to transmit the first cache block based on the first state being secondary shared.

15. The coherent agent circuit as recited in claim 12 wherein the message indicates that the coherent agent circuit is to transmit the first cache block to the different coherent agent circuit based on the first state being primary shared, and wherein the message indicates that the coherent agent circuit is to transmit the first cache block even in the event that the first state is secondary shared.

16. An apparatus comprising:
a

Assignees

• Apple Inc

Inventors

• Vash James
• Garg Gaurav
• Lilly Brian P
• Gunna Ramesh B
• Hutsell Steven R
• Levy-Rubin Lital
• Hammarlund Per H
• Kaushikkar Harshavardhan

Classifications

• G06F12/0815 Primary

  Cache consistency protocols · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F12/0824 Primary

  Distributed directories, e.g. linked lists of caches · CPC title

• G06F2212/1024

  Latency reduction · CPC title