Memory error tracking and logging

Patent metadata

Field	Value
Publication number	US-11934265-B2
Application number	US-202217804950-A
Country	US
Kind code	B2
Filing date	Jun 1, 2022
Priority date	Feb 4, 2022
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.

First claim

What is claimed is:

1. An apparatus, comprising:
one or more processors configured to execute program instructions;
a memory cache;
memory cache controller circuitry configured to:
cache data operated on by the one or more processors in the memory cache;
track, using multiple tracking circuit entries, numbers of detected correctable errors associated with multiple respective locations of data processed by the memory cache controller circuitry, wherein a given correctable error of the detected correctable errors includes up to a threshold number of bit errors; and
in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location.

2. The apparatus of claim 1 , wherein the memory cache controller circuitry is further configured to:
in response to a determination that a number of valid entries in the tracking circuit entries, that indicate at least one correctable error, meets an occupancy threshold, generate an alert signal.

3. The apparatus of claim 2 , wherein the memory cache controller circuitry is further configured to:
in response to the determination, enable software to access one or more tracking circuit entries.

4. The apparatus of claim 3 , wherein the memory cache controller circuitry is further configured to:
in response to software signaling, deallocate one or more of the tracking circuit entries.

5. The apparatus of claim 1 , wherein the multiple tracking circuit entries include respective client identifier fields that indicate a client associated with a given correctable error.

6. The apparatus of claim 1 , wherein the memory cache controller circuitry is further configured to:
track, using multiple uncorrectable error (UE) tracking circuit entries, detected uncorrectable errors associated with multiple respective locations of data processed by the memory cache controller circuitry.

7. The apparatus of claim 6 , wherein the UE tracking circuit entries include a source field that identifies a source of a given UE.

8. The apparatus of claim 7 , wherein the source field is configured to encode sources that include at least the following sources: a memory error, a memory cache error, and a snoop response.

9. The apparatus of claim 6 , wherein the multiple UE tracking circuit entries are not tagged and wherein the multiple tracking circuit entries for detected correctable errors are tagged with at least a portion of an address for a given location.

10. The apparatus of claim 6 , wherein the apparatus is configured to maintain corruption indicators for data blocks, wherein a corruption indicator indicates that a data block was determined to be corrupted.

11. The apparatus of claim 1 , wherein the apparatus is a computing device that further includes:
a central processing unit;
a display; and
network interface circuitry.

12. A method, comprising:
caching, by memory cache controller circuitry in a memory cache, data operated on by one or more processors;
tracking, using multiple tracking circuit entries, numbers of detected correctable errors associated with multiple respective locations of data processed by the memory cache controller circuitry, wherein a given correctable error of the detected correctable errors includes up to a threshold number of bit errors; and
generating a signal to the one or more processors, in response to detecting a threshold number of correctable errors for a particular location, that identifies the particular location.

13. The method of claim 12 , further comprising:
generating, by the memory cache controller circuitry, an alert signal to software, in response to determining that a number of valid entries in the tracking circuit entries, that indicate at least one correctable error, meets an occupancy threshold, that indicates potential future occupancy issues.

14. The method of claim 13 , further comprising:
enabling, in response to meeting the occupancy threshold, software to access one or more tracking circuit entries.

15. The method of claim 12 , further comprising:
tracking, using multiple uncorrectable error (UE) tracking circuit entries, detected uncorrectable errors associated with multiple respective locations of data processed by the memory cache controller circuitry.

16. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:
one or more processors configured to execute program instructions;
a memory cache;
memory cache controller circuitry configured to:
cache data operated on by the one or more processors in the memory cache;
track, using multiple tracking circuit entries, numbers of detected correctable errors associated with multiple respective locations of data processed by the memory cache controller circuitry, wherein a given correctable error of the detected correctable errors includes up to a threshold number of bit errors; and
in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location.

17. The non-transitory computer readable storage medium of claim 16 , wherein the memory cache controller circuitry is further configured to:
generating an alert signal to software, in response to determining that a number of valid entries in the tracking circuit entries, that indicate at least one correctable error, meets an occupancy threshold, that indicates potential future occupancy issues.

18. The non-transitory computer readable storage medium of claim 17 , wherein the memory cache controller circuitry is further configured to:
in response to meeting the occupancy threshold, enable software to access one or more tracking circuit entries.

19. The non-transitory computer readable storage medium of claim 16 , wherein the memory cache controller circuitry is further configured to:
track, using multiple uncorrectable error (UE) tracking circuit entries, detected uncorrectable errors associated with multiple respective locations of data processed by the memory cache controller circuitry.

20. The non-transitory computer readable storage medium of claim 19 , wherein the multiple UE tracking circuit entries are not tagged and wherein the multiple tracking circuit entries are tagged with at least a portion of an address for a given location.

Assignees

• Apple Inc

Inventors

• Nemati Farid
• Hutsell Steven R
• Kumar Derek R
• Semeria Bernard J
• Vash James
• Nangia Era K
• Mathews Gregory S

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F2212/403

  Error protection encoding, e.g. using parity or ECC codes · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2201/885

  Monitoring specific for caches · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title