Coprocessor context priority

Patent metadata

Field	Value
Publication number	US-11768690-B2
Application number	US-202117532072-A
Country	US
Kind code	B2
Filing date	Nov 22, 2021
Priority date	Sep 11, 2020
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.

First claim

What is claimed is:

1. A system comprising:
a plurality of processors;
a coprocessor coupled to the plurality of processors and configured to execute coprocessor instructions transmitted by the plurality of processors, and wherein the coprocessor includes a plurality of contexts;
a plurality of coprocessor context priority registers, wherein a given coprocessor context priority register of the plurality of coprocessor context priority registers corresponds to a respective context of the plurality of contexts, and wherein a context priority programmed into the given coprocessor context priority register specifies a priority of a thread executing in the respective context for execution bandwidth on the coprocessor;
an arbiter coupled to the plurality of processors and the coprocessor and configured to arbitrate between coprocessor instructions from the plurality of processors to select coprocessor instructions to be transmitted to the coprocessor for execution based on the context priorities programmed into the plurality of coprocessor context priority registers; and
a computer accessible storage medium coupled to the plurality of processors and configured to store a plurality of instructions which, when executed by one or more of the plurality of processors, cause the system to implement a plurality of operations comprising:
programming an initial plurality of context priorities in a table, wherein the initial plurality of context priorities correspond to a plurality of threads that include coprocessor instructions;
programming a particular coprocessor context priority register of the plurality of coprocessor context priority registers based on a given thread of the plurality of threads executing on a corresponding processor of the plurality of processors, wherein programming the particular coprocessor context priority register comprises reading a corresponding priority from the table for the given thread and writing the corresponding priority to the particular coprocessor context priority register;
monitoring operation of the plurality of threads; and
based on the operation of the plurality of threads, dynamically modifying one or more of the initial plurality of context priorities in the table.

2. The system as recited in claim 1 wherein a first thread of the plurality of threads has a deadline for completion, and wherein a first context priority of the initial plurality of context priorities is derived from the deadline.

3. The system as recited in claim 2 wherein dynamically modifying one or more of the initial plurality of context priorities is based on the first thread completing execution within a threshold of the deadline.

4. The system as recited in claim 3 wherein the threshold is measured based on an average duty cycle of the first thread observed in the monitoring.

5. The system as recited in claim 2 wherein a second thread of the plurality of threads has a software-assigned context priority, and wherein a corresponding initial context priority of the initial plurality of context priorities is mapped from the software-assigned context priority.

6. The system as recited in claim 1 wherein, during a context switch to a first context on a first processor of the plurality of processors, a second plurality of instructions executed by the first processor cause the first processor to write a first context priority corresponding to the first context to a first coprocessor context priority register of the plurality of coprocessor context priority registers.

7. The system as recited in claim 1 wherein the arbiter is configured to implement a weighted round robin arbitration, and wherein the arbiter is configured to map the context priorities from the plurality of coprocessor context priority registers to a plurality of weights.

8. The system as recited in claim 7 wherein the arbiter is configured to map a plurality of ranges of the coprocessor context priorities to the plurality of weights, wherein context priorities within a given range of the plurality of ranges map to a same weight of the plurality of weights.

9. The system as recited in claim 8 wherein at least one of the plurality of ranges differs in size from at least another one of the plurality of ranges.

10. The system as recited in claim 8 wherein a first range of the plurality of ranges includes a maximum value of the context priorities and is larger in size than a second range of the plurality of ranges that includes a minimum value of the context priorities.

11. The system as recited in claim 10 wherein a third range of the plurality of ranges is smaller in size than a fourth range of the plurality of ranges and larger in size than the second range.

12. The system as recited in claim 8 wherein the plurality of weights are inversely proportional to the context priorities.

13. A method comprising:
programming an initial plurality of context priorities in a table, wherein the initial plurality of context priorities correspond to a plurality of threads that include coprocessor instructions, wherein the coprocessor instructions are executed by a coprocessor coupled to a plurality of processors, wherein the coprocessor includes a plurality of contexts that correspond to a plurality of coprocessor context priority registers, and wherein a context priority programmed into a given coprocessor context priority register specifies a priority for execution bandwidth on the coprocessor, the priority corresponding to a thread executing in a respective context of the plurality of contexts;
programming a particular coprocessor context priority register of the plurality of coprocessor context priority registers based on a given thread of the plurality of threads executing on the plurality of processors, wherein programming the particular coprocessor context priority register comprises reading a corresponding priority from the table for the given thread and writing the corresponding priority to the particular coprocessor context priority register;
arbitrating between coprocessor instructions from the plurality of processors to select coprocessor instructions to be transmitted to the coprocessor for execution based on the context priorities programmed into the plurality of coprocessor context priority registers;
monitoring operation of the plurality of threads; and
based on the operation of the plurality of threads, dynamically modifying one or more of the initial plurality of context priorities in the table.

14. The method as recited in claim 13 wherein a first thread of the plurality of threads has a deadline for completion, and the method further comprises deriving a first context priority of the initial plurality of context priorities from the deadline.

15. The method as recited in claim 14 wherein dynamically modifying one or more of the initial plurality of context priorities is based on the first thread completing execution within a threshold of the deadline.

16. The method as recited in claim 15 wherein the threshold is measured based on an average duty cycle of the first thread observed in the monitoring.

17. The method as recited in claim 14 wherein a second thread of the plurality of threads has a software-assigned priority, and the method further comprises mapping a corresponding initial context priority of the initial plurality of context priorities from the software-assigned priority.

18. The method as recited in claim 13 wherein the arbitrating is based on a weighted round robin arbitration, and the method further comprises mapping the context priorities from the plurality of cop

Assignees

• Apple Inc

Inventors

• Kesiraju Aditya
• Beaumont-Smith Andrew J
• Lilly Brian P
• Vash James
• Kassoff Jason M
• Potnuru Krishna C
• Bhuyar Rajdeep L
• Chachick Ran A
• Huberty Tyler J
• Kumar Derek R

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3877 Primary

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title