Scalable system on a chip

Patent metadata

Field	Value
Publication number	US-11934313-B2
Application number	US-202217821296-A
Country	US
Kind code	B2
Filing date	Aug 22, 2022
Priority date	Aug 23, 2021
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

First claim

What is claimed is:

1. A system, comprising:
a plurality of processor cores;
a plurality of graphics processing units;
a plurality of peripheral devices distinct from the processor cores and the graphics processing units;
a plurality of memory controller circuits configured to interface with a system memory; and
an interconnect fabric configured to provide communication between the memory controller circuits and the processor cores, the graphics processing units, and the peripheral devices;
wherein the processor cores, the graphics processing units, the peripheral devices and the memory controller circuits are configured to communicate via a unified memory architecture in which a given page within a unified address space defined by the unified memory architecture is distributed among the plurality of memory controller circuits; and
wherein the processor cores, the graphics processing units, the peripheral devices, the memory controller circuits, and the interconnect fabric are included in a system on a chip (SOC) integrated onto one or more co-packaged semiconductor dies.

2. The system of claim 1 , wherein the processor cores, the graphics processing units, and the peripheral devices are configured to access any address within the unified address space defined by the unified memory architecture.

3. The system of claim 2 , wherein the unified address space is a virtual address space distinct from a physical address space provided by the system memory.

4. The system of claim 1 , wherein the unified memory architecture provides a common set of semantics for memory access by the processor cores, the graphics processing units, and the peripheral devices.

5. The system of claim 4 , wherein the semantics include memory ordering properties.

6. The system of claim 4 , wherein the semantics include quality of service attributes.

7. The system of claim 4 , wherein the semantics include cache coherency.

8. The system of claim 1 , wherein the memory controller circuits include respective interfaces to one or more memory devices that are mappable to random access memory.

9. The system of claim 8 , wherein the memory devices comprise dynamic random access memory (DRAM).

10. The system of claim 1 , further comprising one or more levels of cache between the processor cores, the graphics processing units, the peripheral devices, and the system memory.

11. The system of claim 10 , wherein the memory controller circuits include respective memory caches interposed between the interconnect fabric and the system memory, wherein the respective memory caches are one of the one or more levels of cache.

12. The system of claim 1 , further comprising a plurality of directories configured to track a coherency state of subsets of the unified address space, wherein the plurality of directories are distributed in the system.

13. The system of claim 12 , wherein the plurality of directories are distributed to the memory controller circuits.

14. The system of claim 1 , wherein a given memory controller circuit of the memory controller circuits comprises a directory configured to track a plurality of cache blocks that correspond to data in a portion of the system memory to which the given memory controller circuit interfaces, wherein the directory is configured to track which of a plurality of caches in the system are caching a given cache block of the plurality of cache blocks, wherein the directory is precise with respect to memory requests that have been ordered and processed at the directory even in the event that the memory requests have not yet completed in the system.

15. The system of claim 14 , wherein the given memory controller circuit is configured to issue one or more coherency maintenance commands for the given cache block based on a memory request for the given cache block, wherein the one or more coherency maintenance commands include a cache state for the given cache block in a corresponding cache of the plurality of caches, wherein the corresponding cache is configured to delay processing of a given coherency maintenance command based on the cache state in the corresponding cache not matching the cache state in the a given coherency maintenance command.

16. The system of claim 14 , wherein a first cache is configured to store the given cache block in a primary shared state and a second cache is configured to store the given cache block in a secondary shared state, and wherein the given memory controller circuit is configured to cause the first cache transfer the given cache block to a requestor based on a memory request of the requestor and the primary shared state in the first cache.

17. The system of claim 14 , wherein the given memory controller circuit is configured to issue one of a first coherency maintenance command and a second coherency maintenance command to a first cache of the plurality of caches based on a type of a first memory request, wherein the first cache is configured to forward a first cache block to a requestor that issued the first memory request based on the first coherency maintenance command, and wherein the first cache is configured to return the first cache block to the given memory controller circuit based on the second coherency maintenance command.

18. A method comprising:
communicating, in a system on a chip (SOC), using a unified memory architecture over a communication fabric among a plurality of memory controllers, a plurality of processors, a plurality of graphics processing units, a plurality of peripheral circuits, wherein the unified memory architecture provides a common set of semantics for memory access by the processors, the graphics processing units, and the peripheral circuits, wherein the memory controllers, the processors, the graphics processing units, the peripheral circuits, and the communication fabric are integrated onto one or more co-packaged semiconductor dies; and
distributing, in the SoC, a given page within a unified address space defined by the unified memory architecture among the plurality of memory controllers for storage in memory.

19. The method of claim 18 , wherein the semantics include memory ordering properties.

20. The method of claim 18 , wherein the semantics include quality of service attributes.

21. The method of claim 18 , wherein the semantics include memory coherency.

Assignees

• Apple Inc

Inventors

• Hammarlund Per H
• Zimet Lior
• Vash James
• Garg Gaurav
• Kolor Sergio
• Kaushikkar Harshavardhan
• Gunna Ramesh B
• Hutsell Steven R

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/128

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title