Scalable system on a chip

Patent metadata

Field	Value
Publication number	US-12007895-B2
Application number	US-202217821305-A
Country	US
Kind code	B2
Filing date	Aug 22, 2022
Priority date	Aug 23, 2021
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

First claim

What is claimed is:

1. A system, comprising:
a plurality of processor cores;
a plurality of graphics processing units;
a plurality of peripheral devices distinct from the processor cores and the graphics processing units;
one or more memory controller circuits configured to interface with a system memory; and
an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, the graphics processing units, and the peripheral devices;
wherein the interconnect fabric comprises at least two networks having heterogeneous operational characteristics; and
wherein the processor cores, the graphics processing units, the peripheral devices, the one or more memory controller circuits, and the interconnect fabric are included in a system on a chip (SOC) integrated onto one or more co-packaged semiconductor dies.

2. The system of claim 1 , wherein the interconnect fabric is configured to allow interconnection of a variable number of processor cores, graphics processing units, peripheral devices, or memory controller circuits.

3. The system of claim 1 , wherein the at least two networks include a coherent network interconnecting the processor cores and the one or more memory controller circuits.

4. The system of claim 1 , wherein the at least two networks include a relaxed-ordered network coupled to the graphics processing units and the one or more memory controller circuits.

5. The system of claim 4 , wherein the peripheral devices include a subset of devices, wherein the subset includes one or more of a machine learning accelerator circuit or a relaxed-order bulk media device, and wherein the relaxed-ordered network is further coupled to the subset of devices to the one or more memory controller circuits.

6. The system of claim 4 , wherein the at least two networks include an input-output network coupled to interconnect the peripheral devices and the one or more memory controller circuits.

7. The system of claim 6 , wherein the peripheral devices include one or more real-time devices.

8. The system of claim 1 , wherein the at least two networks comprise a first network that comprises one or more characteristics to reduce latency compared to a second network of the at least two networks.

9. The system of claim 8 , wherein the one or more characteristics comprise a shorter route than the second network.

10. The system of claim 8 , wherein the one or more characteristics comprise wiring in metal layers that have one or more lower latency characteristics than metal layers used for the wiring for the second network.

11. The system of claim 1 , wherein the at least two networks comprise a first network that comprises one or more characteristics to increase bandwidth compared to a second network of the at least two networks.

12. The system of claim 11 , wherein the one or more characteristics comprise an interconnect using a larger number of wires compared to an interconnect for the second network.

13. The system of claim 11 , wherein the one or more characteristics comprise wiring in metal layers that are denser than metal layers used for the wiring for the second network.

14. The system of claim 1 , wherein interconnect topologies employed by the at least two networks include at least one of a star topology, a mesh topology, a ring topology, a tree topology, a fat tree topology, a hypercube topology, or a combination of one or of the topologies.

15. The system of claim 1 , wherein the operational characteristics employed by the at least two networks include at least one of strongly-ordered memory coherence or relaxed-ordered memory coherence.

16. The system of claim 4 , wherein the at least two networks are physically and logically independent.

17. The system of claim 1 , wherein the at least two networks are physically separate in a first mode of operation, and wherein a first network of the at least two networks and a second network of the at least two networks are virtual and share a single physical network in a second mode of operation.

18. A system on a chip (SOC), the SOC comprising:
a plurality of processor cores;
a plurality of graphics processing units;
a plurality of peripheral devices;
one or more memory controller circuits; and
an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices;
wherein the interconnect fabric comprises at least a first network and a second network, wherein the first network comprises one or more characteristics to reduce latency compared to the second network of the at least two networks, and wherein a given one of the one or more memory controller circuits is coupled to the first and second networks and configured to receive memory requests from both of the first and second networks; and
wherein the processor cores, the graphics processing units, the peripheral devices, the one or more memory controller circuits, and the interconnect fabric are integrated onto one or more co-packaged semiconductor dies.

19. The SOC of claim 18 , wherein the one or more characteristics comprise a shorter route for the first network over a surface of the semiconductor die than a route of the second network.

20. The SOC of claim 18 , wherein the one or more characteristics comprise wiring in metal layers have one or more lower latency characteristics than metal layers used for the wiring for the second network.

21. The SOC of claim 18 , wherein the second network comprises one or more second characteristics to increase bandwidth compared to the first network.

22. The SOC of claim 21 , wherein the one or more second characteristics comprise an interconnect having more wires compared to an interconnect in the second network.

23. The SOC of claim 21 , wherein the one or more second characteristics comprise wiring in metal layers that are denser than metal layers used for the wiring for the second network.

24. A system on a chip (SOC), the SOC comprising:
a plurality of processor cores;
a plurality of graphics processing units;
a plurality of peripheral devices;
one or more memory controller circuits; and
an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices;
wherein the interconnect fabric comprises at least a first network and a second network, wherein the first network is physically and logically independent from the second network, and wherein the first and second networks have heterogeneous interconnect topologies; and
wherein the processor cores, the graphics processing units, the peripheral devices, the one or more memory controller circuits, and the interconnect fabric are integrated onto one or more co-packaged semiconductor dies.

25. The SOC of claim 24 , wherein the first network and the second network are physically separate in a first mode of operation, and wherein a first network of the at least two networks and a second network of the at least two networks are virtual and share a single physical network in a second mode of operation.

Assignees

• Apple Inc

Inventors

• Hammarlund Per H
• Tamari Eran
• Zimet Lior
• Kolor Sergio
• Tota Sergio V
• Lahav Sagi
• Vash James
• Garg Gaurav
• Redshaw Jonathan M
• Hutsell Steven R
• Kaushikkar Harshavardhan
• Fukami Shawn M

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/128

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title