DSB operation with excluded region

Patent metadata

Field	Value
Publication number	US-11720360-B2
Application number	US-202117469504-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	Sep 11, 2020
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

First claim

What is claimed is:

1. A system, comprising:
a plurality of processors, wherein the plurality of processors each include one or more registers programmable to define an exclusion region of a memory address space, and wherein the plurality of processors are communicatively coupled, wherein:
a first processor of the plurality of processors is configured to issue a first data barrier operation request responsive to executing a data barrier instruction;
a second processor of the plurality of processors is configured to, based on receiving the first data barrier operation request from the first processor:
ensure that outstanding load/store operations executed by the second processor that are directed to addresses outside of the exclusion region have been completed; and
respond to the first processor that the first data barrier operation request is complete at the second processor, even in the case that one or more load/store operations directed to addresses within the exclusion region are outstanding and not complete when the second processor responds that the first data barrier operation request is complete.

2. The system of claim 1 , wherein the second processor is configured to:
associate a load/store operation with an indication that identifies whether the load/store operation is directed to an address within the exclusion region, wherein to ensure that the outstanding load/store operations directed to addresses outside of the exclusion region have been completed, the second processor is further configured to determine whether there is an outstanding load/store operation with an indication identifying that the outstanding load/store operation is directed to an address outside the exclusion region.

3. The system of claim 1 , wherein the second processor is configured to:
determine whether an outstanding load/store operation is directed to an address within the exclusion region based on a comparison between an address that is identified by the outstanding load/store operation and an address range associated with the exclusion region.

4. The system of claim 1 , wherein the second processor is configured to, in response to receiving a second data barrier operation request that instructs the second processor to include outstanding load/store operations directed to addresses within the exclusion region when considering when to respond to the first processor:
ensure that all outstanding load/store operations executed by the second processor have been completed; and
respond to the first processor that the second data barrier operation request is complete at the second processor.

5. The system of claim 1 , wherein the second processor is configured to:
while processing the first data barrier operation request, receive a second data barrier operation request from a third processor of the plurality of processors; and
in response to the second data barrier operation request being of a different type than the first data barrier operation request, concurrently process the first and second data barrier operation requests.

6. The system of claim 1 , wherein the second processor is configured to:
while processing the first data barrier operation request, receive a second data barrier operation request from a third processor of the plurality of processors; and
in response to the second data barrier operation request being of the same type as the first data barrier operation request, serially process the first and second data barrier operations.

7. The system of claim 1 , wherein the exclusion region includes a set of addresses mapped to an I/O device external to the plurality of processors.

8. The system of claim 1 , wherein the first processor is configured to issue two different types of data barrier operation requests, and wherein the second processor is configured to:
maintain first and second flush pointers, each of which identifies a respective load/store operation at which to flush a load/store unit of the second processor;
in response to a detection that the first data barrier operation request is a first one of the two different types, flush the load/store unit at the first flush pointer; and
in response to a detection that the first data barrier operation request is a second one of the two different types, flush the load/store unit at the second flush pointer.

9. The system of claim 8 , wherein the second processor is configured to:
in response to completing an outstanding load/store operation, modify the first flush pointer to identify a load/store operation occurring next after the outstanding load/store operation in instruction order.

10. The system of claim 8 , wherein the second processor is configured to:
in response to initiating a load/store operation that is directed to an address within the exclusion region, set the first flush pointer to a valid state that permits the second processor to flush the load/store unit at the first flush pointer.

11. A method, comprising:
receiving, by a first processor, a first data barrier operation request from a second processor;
based on receiving the first data barrier operation request from the second processor, the first processor ensuring that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region of a memory address space have been completed, wherein the first processor and the second processor each include one or more registers programmable to define the exclusion region of the memory address space; and
responding, by the first processor, to the second processor that the first data barrier operation request is complete at the first processor, even in the case that one or more load/store operations directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the first data barrier operation request is complete.

12. The method of claim 11 , further comprising:
maintaining, by the first processor, a first flush pointer that identifies a location within an instruction sequence at which to flush a load/store unit of the first processor in response to receiving the first data barrier operation request; and
maintaining, by the first processor, a second flush pointer that identifies a different location within the instruction sequence at which to flush the load/store unit in response to receiving a data barrier operation request of a different type than the first data barrier operation request.

13. The method of claim 12 , further comprising:
initiating, by the first processor, a store operation directed to a memory address within the exclusion region; and
in response to initiating the store operation, the first processor updating the first flush pointer to identify a load/store operation occurring next after the store operation in instruction order.

14. The method of claim 12 , further comprising:
completing, by the first processor, a load/store operation; and
in response to completing the load/store operation, the first processor updating the first flush pointer to identify a load/store operation occurring next after the completed load/store operation in instruction order.

15. The method of claim 11 , further comprising:
before receiving the first data barrier operation request, the first processor receiving a second data barrier operation request that instructs the first processor to complete outstanding load/store operations directed to addresses within the exclusion region before responding that the second data barrier operation request is complete at the first processor, wherein the responding to the second pr

Assignees

• Apple Inc

Inventors

• Gonion Jeff
• Kelm John H
• Vash James
• Kanapathipillai Pradeep
• Agarwal Mridul
• Levinsky Gideon N
• Russo Richard F
• Tsay Christopher M

Classifications

• G06F9/30087 Primary

  Synchronisation or serialisation instructions · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title