Multiple independent on-chip interconnect

Patent metadata

Field	Value
Publication number	US-12561267-B2
Application number	US-202318309192-A
Country	US
Kind code	B2
Filing date	Apr 28, 2023
Priority date	Apr 16, 2021
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

First claim

What is claimed is:

1 . An apparatus comprising:
a plurality of agent circuits including a first subset of agent circuits and a second subset of agent circuits, wherein
agent circuits of the first subset are heterogenous with respect to agent circuits of the second subset,
the first subset comprises a plurality of processor clusters,
the second subset comprises a plurality of graphics processing unit (GPU) circuits, and
a given processor cluster comprises two or more central processing unit (CPU) circuits coupled to a given last level cache;
one or more memory controllers configured to communicate with a system memory; and a plurality of network switches including:
a first subset of network switches interconnected to form a first network coupled between the first subset of agent circuits and the one or more memory controllers, wherein the one or more memory controllers are directly coupled to the first network, and wherein the given processor cluster of the plurality of processor clusters is configured to access the system memory via the first network; and
a second subset of network switches interconnected to form a second network coupled between the second subset of agent circuits and the one or more memory controllers, wherein the one or more memory controllers are directly coupled to the second network, and wherein a given GPU circuit of the plurality of GPU circuits is configured to access the system memory via the second network, and wherein the first and second networks are logically and physically independent from one another.

2 . The apparatus of claim 1 , further comprising:
a third subset of agent circuits that are heterogenous with respect to ones of the first and second subsets of agent circuits, and wherein the plurality of network switches further includes
a third subset of network switches interconnected to form a third network coupled between the third subset of agent circuits and the one or more memory controllers, wherein the third network is logically and physically independent from the first and second networks.

3 . The apparatus of claim 2 , wherein a number of physical channels of one of the first, second, and third networks is different from that of at least one other one of the first, second, and third networks.

4 . The apparatus of claim 2 , wherein ones of the first, second and third networks are configured to implement a plurality of virtual channels, wherein at least one of the plurality of virtual channels has a different quality-of-service than at least one other one of the plurality of virtual channels.

5 . The apparatus of claim 1 , wherein the first and second networks include corresponding ones of a plurality of network interfaces configured to convert communications between a given one of the plurality of agent circuits and a given one of the plurality of network switches in accordance with a format of a given one of the first and second networks.

6 . The apparatus of claim 1 , wherein the second subset of network switches includes at least one network switch configured to facilitate communications between at least one of the first subset of agent circuits and ones of the second subset of agent circuits via the second network.

7 . The apparatus of claim 1 , wherein the plurality of agent circuits, the plurality of network switches, and the one or more memory controllers are implemented on a single integrated circuit die.

8 . A system comprising:
an integrated circuit implementing a system-on-a-chip (SOC), wherein the SOC includes:
a plurality of processor clusters, wherein a given processor cluster comprises two or more central processing unit (CPU) circuits coupled to a given last level cache;
a plurality of peripheral circuits including at least one interface circuit configured to communicate with devices external to the SOC;
a plurality of graphics processing unit (GPU) circuits;
a plurality of memory controllers configured to communicate with a system memory; and
a plurality of network switches including:
a first subset of network switches interconnected to form a CPU network coupled between the plurality of processor clusters and the plurality of memory controllers, wherein the plurality of memory controllers are directly coupled to the CPU network, and wherein the given processor cluster of the plurality of processor clusters is configured to communicate with the system memory via the CPU network; and
a second subset of network switches configured to form an input/output (I/O) network coupled between the plurality of peripheral circuits and the plurality of memory controllers, wherein the plurality of memory controllers are directly coupled to the I/O network, and wherein a given peripheral circuit of the plurality of peripheral circuits is configured to communicate with the system memory via the I/O network; and
a third subset of network switches interconnected to form a GPU network coupled between the plurality of memory controllers and the plurality of GPU circuits, wherein the plurality of memory controllers are directly coupled to the GPU network, and wherein a given GPU circuit of the plurality of GPU circuits is configured to communicate with the system memory via the GPU network;
wherein the CPU network, the GPU network and the I/O network are logically and physically independent from one another.

9 . The system of claim 8 , wherein the I/O network includes at least one switch coupled to the CPU network and configured to facilitate communications between the I/O network and the CPU network.

10 . The system of claim 8 , wherein the CPU network and the I/O network are implemented using a ring network topology, and wherein the GPU network is implemented using a mesh network topology.

11 . The system of claim 8 , wherein the GPU network is a non-coherent network.

12 . The system of claim 8 , wherein the CPU network and the I/O network support cache coherency.

13 . The system of claim 8 , wherein the plurality of peripheral circuits includes one or more of:
an image signal processing circuit; a video encoder/decoder circuit; an audio processing circuit; and a media access controller circuit.

14 . A method comprising:
a memory controller communicating with a system memory; communicating with the system memory, via the memory controller and a first network having a first plurality of network switches, using a plurality of processor clusters of an electronic circuit, wherein a given processor cluster of the plurality of processor clusters includes two or more central processing unit (CPU) circuits coupled to a given last level cache and wherein the memory controller is directly coupled to the first network; and communicating with the system memory, via the memory controller and a second network having a second plurality of network switches, using a plurality of graphics processing unit (GPU) circuits of the electronic circuit, wherein the memory controller is directly coupled to the second network and wherein the first and second networks are physically independent of one another; wherein communications conducted on the first network are conducted logically independent of communications conducted on the second network, and wherein communications conducted on the second network are conducted logically independent of communications conducted on the first network.

15 . The method of claim 14 , further comprising:
communicating with the system memory, via the memory controller and a third network having a third plurality of network switches, using a plurality of peripheral circuits of the electronic circuit, wherei

Assignees

• Apple Inc

Inventors

• Kolor Sergio
• Tota Sergio V
• Zemer Tzach
• Lahav Sagi
• Redshaw Jonathan M
• Hammarlund Per H
• Tamari Eran
• Vash James
• Garg Gaurav
• Zimet Lior
• Kaushikkar Harshavardhan
• Fishwick Steven
• Hutsell Steven R
• Fukami Shawn M

Classifications

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F15/17375

  One dimensional, e.g. linear array, ring · CPC title

• G06F15/17381

  Two dimensional, e.g. mesh, torus · CPC title

• G06F2213/0038

  System on Chip · CPC title

• G06F2115/02

  System on chip [SoC] design · CPC title