Implicit program order
US-11977891-B2 · May 7, 2024 · US
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Smith Aaron L patents
Smith Aaron L is listed as an inventor on 62 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Smith Aaron L |
| Total patents | 62 |
| First publication | May 7, 2015 |
| Latest publication | May 7, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Instruction block allocation
US-11755484-B2 · Sep 12, 2023 · US
Coupling wide memory interface to wide write back paths
US-11726912-B2 · Aug 15, 2023 · US
Out-of-order block-based processors and instruction schedulers using ready state data indexed by instruction position identifiers
US-11687345-B2 · Jun 27, 2023 · US
Generation and use of memory access instruction order encodings
US-11681531-B2 · Jun 20, 2023 · US
Hybrid block-based processor and custom function blocks
US-11449342-B2 · Sep 20, 2022 · US
Block-based processor core composition register
US-11126433-B2 · Sep 21, 2021 · US
Incremental scheduler for out-of-order block ISA processors
US-11106467-B2 · Aug 31, 2021 · US
Coupling wide memory interface to wide write back paths
US-2021216454-A1 · Jul 15, 2021 · US
Distinct system registers for logical processors
US-11016770-B2 · May 25, 2021 · US
Recent patents
Latest publications not already listed above.
Coupling wide memory interface to wide write back paths
US-10963379-B2 · Mar 30, 2021 · US
Dense read encoding for dataflow ISA
US-10936316-B2 · Mar 2, 2021 · US
Register read/write ordering
US-10871967-B2 · Dec 22, 2020 · US
Debug support for block-based processor
US-10776115-B2 · Sep 15, 2020 · US
Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
US-10768936-B2 · Sep 8, 2020 · US
Initiating instruction block execution using a register access instruction
US-10678544-B2 · Jun 9, 2020 · US
Broadcast channel architectures for block-based processors
US-10452399-B2 · Oct 22, 2019 · US
Multimodal targets in a block-based processor
US-10445097-B2 · Oct 15, 2019 · US
Verifying branch targets
US-10409606-B2 · Sep 10, 2019 · US
Coupling wide memory interface to wide write back paths
US-2019236009-A1 · Aug 1, 2019 · US
Write nullification
US-10198263-B2 · Feb 5, 2019 · US
Dynamic generation of null instructions
US-10180840-B2 · Jan 15, 2019 · US
Multi-nullification
US-2018329708-A1 · Nov 15, 2018 · US
Instruction block address register
US-10095519-B2 · Oct 9, 2018 · US
Store nullification in the target field
US-10061584-B2 · Aug 28, 2018 · US
Multi-nullification
US-10031756-B2 · Jul 24, 2018 · US
Out-of-order block-based processor
US-2018032344-A1 · Feb 1, 2018 · US
Transactional register file for a processor
US-2018032335-A1 · Feb 1, 2018 · US
Load-store queue for multiple processor cores
US-2017371660-A1 · Dec 28, 2017 · US
Load-store queue for block-based processor
US-2017371659-A1 · Dec 28, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Microsoft Technology Licensing Llc | 61 |
| Microsoft Corp | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/3858 | 62 |
| G06F9/3854 | 62 |
| G06F9/3836 | 54 |
| G06F9/30043 | 50 |
| G06F9/3005 | 49 |