Broadcast channel architectures for block-based processors

Patent metadata

Field	Value
Publication number	US-10452399-B2
Application number	US-201615074938-A
Country	US
Kind code	B2
Filing date	Mar 18, 2016
Priority date	Sep 19, 2015
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Apparatus and methods are disclosed for example computer processors that are based on a hybrid dataflow execution model. In particular embodiments, a processor core in a block-based processor comprises: one or more functional units configured to perform functions using one or more operands; an instruction window comprising buffers configured to store individual instructions for execution by the processor core, the instruction window including one or more operand buffers for an individual instruction configured to store operand values; a control unit configured to execute the instructions in the instruction window and control operation of the one or more functional units; and a broadcast value store comprising a plurality of buffers dedicated to storing broadcast values, each buffer of the broadcast value store being associated with a respective broadcast channel from among a plurality of available broadcast channels.

First claim

We claim:

1. A processor core in a block-based processor, the processor core comprising:
at least one functional unit comprising at least one integer ALU, floating point ALU, or shift/rotate logic configured to receive one or more operands;
an instruction window comprising buffers configured to store individual instructions for execution by the processor core; and
circuitry controlling operation of the at least one functional unit during execution of a respective instruction,
wherein the instruction window includes, for the respective instruction, (a) a buffer dedicated to storing the respective instruction; (b) a buffer dedicated to storing one or more operands for use by the respective instruction; and (c) a memory element or buffer that stores control bits from monitoring a broadcast control bus shared among instructions in the instruction window and, when instructed by a control signal generated from the respective instruction by the circuitry, detect values broadcast on a broadcast data bus and conditionally copies the values into the buffer dedicated to storing the operand for use by the respective instruction.

2. The processor core of claim 1 , wherein the buffer dedicated to storing one or more operands for use by the respective instruction is dedicated to storing a left operand or a right operand, and wherein the memory element or buffer that stores control bits from monitoring the broadcast control bus shared among instructions in the instruction window is configured to copy the one or more values into the buffer dedicated to storing the operand when operand type data from the values broadcast on the broadcast control bus indicate that the values being broadcast on the broadcast data bus are to be used as the left operand or the right operand.

3. The processor core of claim 2 , wherein the instruction window further includes, for the respective instruction to be executed by the processor core, (d) a buffer dedicated to storing a predicate operand for use by the respective instruction, and wherein the memory element or buffer that stores control bits from monitoring the broadcast control bus shared among instructions in the instruction window is further configured to conditionally copy one or more of the values from the broadcast data bus into the buffer dedicated storing the predicate operand when operand type data from the values broadcast on the broadcast control bus indicate that the values being broadcast are to be used as a predicate operand.

4. The processor core of claim 1 , wherein the values broadcast on the broadcast control bus include one or more broadcast channel identifiers that identify which one of multiple available broadcast channels the values being currently broadcast on the broadcast data bus are associated with.

5. The processor core of claim 4 , wherein the memory element or buffer that stores control bits from monitoring the broadcast control bus shared among instructions in the instruction window is configured to copy the one or more values into the buffer dedicated to storing the one or more operands when the broadcast channel identified by the broadcast channel identifiers matches a broadcast channel specified by the respective instruction.

6. The processor core of claim 1 , wherein the memory element or buffer that stores control bits from monitoring the broadcast control bus shared among instructions in the instruction window includes a set of control memory elements, a first memory element of the set storing a bit value indicating whether the listening unit is waiting for a broadcast on the broadcast data bus and a second memory element of the set storing a bit value indicating whether the listening unit has detected and copied data from the broadcast data bus.

7. The processor core of claim 6 , wherein the set of control memory elements further includes a third memory element storing one or more bit values that identify a broadcast channel for which the memory element or buffer that stores control bits from monitoring the broadcast control bus shared among instructions in the instruction window is waiting.

8. The processor core of claim 1 , wherein the respective instruction includes broadcast identifier (ID) data identifying a broadcast channel for which the memory element or buffer that stores control bits from monitoring the broadcast control bus shared among instructions in the instruction window is to monitor and operand type data indicating an operand type of the data broadcast on the broadcast data bus.

9. A block-based processing system, comprising:
a plurality of processor cores, a respective one of the processor cores comprising:
one or more functional units comprising at least one integer ALU, floating point ALU, or shift/rotate logic to perform functions for one or more instructions,
an instruction window comprising buffers configured to store individual instructions for execution by the processor core, the instruction window further comprising one or more operand buffers for the individual instructions configured to store operand values, and
circuitry controlling operation of the one or more functional units during execution of a respective instruction; and

a broadcast value store comprising a plurality of buffers dedicated to storing broadcast values, each buffer of the broadcast value store being associated with a respective broadcast channel from among a plurality of available broadcast channels.

10. The block-based processing system of claim 9 , wherein the instruction window is one of a plurality of instruction windows in the respective one of the processor cores, and wherein each buffer of the broadcast store is associated with both a respective broadcast channel from among the plurality of available broadcast channels and an associated one of the plurality of instruction windows.

11. The block-based processing system of claim 9 , wherein, during execution of the respective instruction, the circuitry controlling operation of the one or more functional units during execution of the respective instruction selectively fetches and sends to the one or more functional units either an operand value from one of the operand buffers in the instruction window for the instruction, or an operand value from one of the buffers of the broadcast value store, the selective use being dependent on whether the instruction specifies use of one of the broadcast channels for an operand for the instruction.

12. The block-based processing system of claim 9 , wherein the buffers for the individual instruction further include a predicate operand buffer configured to store a predicate operand value, and
wherein the circuitry controlling operation of the one or more functional units during execution of the respective instruction is configured to selectively use as a predicate for the individual instruction either a predicate value from the predicate operand buffer or a predicate value from one of the buffers of the broadcast value store, the selective use being dependent on whether the individual instruction specifies use of one of the broadcast channels for an operand for the individual instruction and also whether an operand type value at the specified one of the broadcast channels indicates that the channel is for a predicate operand.

13. The block-based processing system of claim 9 , wherein at least some of the broadcast values stored in the broadcast value store are available for operand use to all instructions in the instruction window.

14. The block-based processing system of claim 9 , wherein the broadcast values stored in a buffer of the broadcast value store include operand type values indicative of an o

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Burger Douglas C
• Smith Aaron L

Classifications

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30167

  of immediate specifier, e.g. constants · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3016 Primary

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title