Verifying branch targets

Patent metadata

Field	Value
Publication number	US-10409606-B2
Application number	US-201514752356-A
Country	US
Kind code	B2
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

Apparatus and methods are disclosed for implementing bad jump detection in block-based processor architectures. In one example of the disclosed technology, a block-based processor includes one or more block-based processing cores configured to fetch and execute atomic blocks of instructions and a control unit configured to, based at least in part on receiving a branch signal indicating a target location is received from one of the instruction blocks, verify that the target location is a valid branch target.

First claim

We claim:

1. An apparatus comprising a processor, the processor comprising:
at least one processing core configured to fetch and execute a current instruction block;
a control unit configured to, based on receiving a branch signal when executing the current instruction block, the branch signal indicating a target location where a next instruction block is stored in memory, verify that an instruction block header stored at the target location conforms to a specification for an instruction block header by:
checking that one or more bits stored at the target location match a specified bit pattern,
verifying that at least one field of the header conforms to an ISA specification for an instruction header, or
checking that one or more bits stored at the target location match a specified bit pattern and verifying that at least one field of the header conforms to the ISA specification for an instruction header; and

when the control unit verifies that the instruction block header does conform to the specification, transfer control of the at least one processing core to the next instruction block stored in memory at the target location.

2. The apparatus of claim 1 , wherein the branch signal includes a memory address of the target location.

3. The apparatus of claim 1 , wherein the control unit is configured to verify that the instruction block header stored at the target location conforms to a specification by checking that one or more bits stored at the target location match an architectural specification for the processor.

4. The apparatus of claim 1 , wherein the control unit is further configured to verify that the target location is at a valid memory address for storing an instruction block.

5. The apparatus of claim 1 , wherein the branch signal is generated by executing a conditional branch instruction by one of the processing cores, and wherein the target location is indicated by a memory location relative to the conditional branch instruction.

6. The apparatus of claim 1 , wherein the processor is implemented as a field programmable gate array, an application-specific integrated circuit, or an integrated circuit.

7. The apparatus of claim 1 , wherein the verifying that the instruction block header stored at the target location conforms to the specification comprises verifying that the first bit at the target location is a one (1).

8. The apparatus of claim 1 , wherein the control unit is further configured to, when the target location is verified to be a valid branch target, initiate execution of the next instruction block.

9. The apparatus of claim 1 , wherein the control unit is further configured to, when the target location is verified to be a valid branch target, execute instructions for handling a branch address exception.

10. The apparatus of claim 1 , wherein the verifying that an instruction block header stored at the target location conforms to a specification for an instruction block header does not comprise checking that one or more bits stored at the target location match a specified bit pattern.

11. The apparatus of claim 1 , wherein the verifying that an instruction block header stored at the target location conforms to a specification for an instruction block header does not comprise verifying that at least one field of the header conforms to the ISA specification for an instruction header.

12. One or more computer-readable storage devices or memory storing computer-executable instructions for a processor, the computer-executable instructions including:
an instruction block storing:
an instruction block header stored at the start of the instruction block and comprising an identifier (ID) field comprising one or more ID bits identifying the instruction block header as a legal branch target location, the ID bits comprising at least one bit that matches a specified bit pattern for the instruction block header; and
at least two instructions.

13. The one or more computer-readable storage devices or memory of claim 12 , wherein each of the at least two instructions comprises bits in a corresponding position as the instruction header ID field that identify the respective instruction as an illegal branch target location.

14. The one or more computer-readable storage devices or memory of claim 12 , wherein the ID field is the least significant bit of a first word of the instruction block header, and wherein the least significant bit of the first word is a one (1).

15. A method of detecting an invalid branch instruction in a processor configured to execute atomic blocks comprising two or more instructions, the method comprising:
with the processor:
fetching and initiating execution of an instruction block;
generating a branch signal by executing an instruction of the instruction block indicating a target location;
based on the receiving the branch signal, verifying whether the target location is a valid branch target by:
checking that one or more bits stored at the target location match a specified bit pattern,
verifying that at least one field of the header conforms to an ISA specification for an instruction header, or
checking that one or more bits stored at the target location match a specified bit pattern and verifying that at least one field of the header conforms to the ISA specification for an instruction header; and

when the verifying indicates an instruction block header is not stored at the target location, initiating branch instruction exception processing.

16. The method of claim 15 , wherein the branch signal includes a memory address of the target location.

17. The method of claim 15 , wherein the verifying whether the target location is a valid branch target further comprises verifying that the target location is at a valid memory address for storing an instruction block.

18. The method of claim 15 , wherein the branch signal is generated by executing a conditional branch instruction by one of the processing cores, and wherein the target location is indicated by a memory location relative to the conditional branch instruction.

19. The method of claim 15 , wherein the fetching and initiating executing, the generating a branch signal, and the verifying the target location are performed using a processor as a field programmable gate array, an application-specific integrated circuit, or an integrated circuit.

20. The method of claim 15 , wherein the checking that one or more bits stored at the target location match an architectural specification comprises verifying that the first bit at the target location is a one (1).

21. The method of claim 15 , wherein the verifying whether the target location is a valid branch target comprises checking that one or more bits stored at the target location match a specified bit pattern but does not comprise verifying that at least one field of the header conforms to an ISA specification for an instruction header.

22. The method of claim 15 , wherein the verifying whether the target location is a valid branch target comprises verifying that at least one field of the header conforms to an ISA specification for an instruction header but does not comprise checking that one or more bits stored at the target location match a specified bit pattern.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Burger Douglas C
• Smith Aaron L
• Gray Jan S

Classifications

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3832

  Value prediction for operands; operand history buffers · CPC title

• G06F9/3844 Primary

  using dynamic branch prediction, e.g. using branch history tables · CPC title

• G06F9/3806 Primary

  using address prediction, e.g. return stack, branch history buffer · CPC title

• G06F9/322 Primary

  for non-sequential address · CPC title