Instruction block allocation

Patent metadata

Field	Value
Publication number	US-11755484-B2
Application number	US-201514752418-A
Country	US
Kind code	B2
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

Apparatus and methods are disclosed for throttling processor operation in block-based processor architectures. In one example of the disclosed technology, a block-based instruction set architecture processor includes a plurality of processing cores configured to fetch and execute a sequence of instruction blocks. Each of the processing cores includes function resources for performing operations specified by the instruction blocks. The processor further includes a core scheduler configured to allocate functional resources for performing the operations. The functional resources are allocated for executing the instruction blocks based, at least in part, on a performance metric. The performance metric can be generated dynamically or statically based on branch prediction accuracy, energy usage tolerance, and other suitable metrics.

First claim

We claim:

1. An apparatus comprising a processor, the processor comprising:
one or more processing cores configured to fetch and execute a sequence of instruction groups, each of the one or more processing cores comprising functional resources performing operations specified by the sequence of instruction groups; and
one or more core schedulers:
allocating processing cores performing at least a portion of operations specified by child instruction groups of the sequence by a respective aggregated confidence rating, for two or more parent instruction groups, of a child instruction group of the child instruction groups, each of the two or more parent instruction groups being on a respective separate instruction path converging on the child instruction group, and
determining the respective aggregated confidence rating by combining confidence ratings for the converging instruction paths of the two or more parent instruction groups of the child instruction group, and consequently according to the respective aggregated confidence rating, initiating execution of the child instruction group prior to initiating execution of at least one of the child instruction group's two or more parent instruction groups.

2. The apparatus of claim 1 , wherein the respective aggregated confidence rating is based at least in part on branch prediction accuracy for one or more branch instructions of the two or more parent instruction groups.

3. The apparatus of claim 1 , wherein the processor further comprises one or more performance counters configured to monitor performance of the processor, and wherein the respective aggregated confidence rating is determined based at least in part on data received from the performance counters.

4. The apparatus of claim 1 , wherein:
the one or more core schedulers are configured to speculatively initiate instruction fetch, instruction decode, or instruction fetch and instruction decode operations for the child instruction group prior to dependencies for the child instruction group being available; and
the one or more core schedulers are configured to inhibit execution of the child instruction group until dependencies for the child instruction group are available.

5. The apparatus of claim 1 , wherein the one or more core schedulers are configured to speculatively initiate fetch, decode, and execute instruction operations for child instruction groups of one or more branches of an instruction group concurrently being fetched, decoded, or executed, based at least in part on the aggregated confidence rating.

6. The apparatus of claim 1 , wherein the one or more core schedulers are configured to, based at least in part on confidence rating increasing, branch to and execute instructions on a processor core that includes previously-fetched, or previously-fetched and previously-decoded, instruction groups.

7. The apparatus of claim 1 , wherein the one or more core schedulers are configured to adjust a number of processor cores, a number of functional resources of processor cores, or a number of processor cores and functional resources of processor cores allocated to executing the sequence of instruction groups based on comparing the aggregated confidence rating to one or more predetermined values.

8. The apparatus of claim 7 , wherein at least one of the processor cores comprises two or more instruction windows, and wherein the one or more core schedulers are configured to allocate more functional resources of the at least one processor core to one of the two or more instruction windows having a higher confidence level.

9. The apparatus of claim 1 , wherein the one or more core schedulers are configured to adjust the number of instruction groups that are prefetched, decoded, or executed based on comparing a confidence rating to one or more predetermined values.

10. The apparatus of claim 1 , wherein at least one of the one or more processing cores is configured to prefetch, decode, or prefetch and decode one or more instruction headers for one or more target instruction groups of a currently executing instruction group.

11. A method performed by a core scheduler for at least two processor cores configured to fetch and execute a sequence of instruction groups, each of the at least two processor cores comprising functional resources for performing operations specified by the sequence of instruction groups, the method comprising:
aggregating confidence ratings of two or more parent instruction groups of a child instruction group to determine an aggregated confidence rating of the child instruction group;
determining that the aggregated confidence rating of the child instruction group is higher than a confidence rating of at least one of the parent instruction groups of the child instruction group, each of the parent instruction groups being on a respective separate instruction path to the child instruction group;
based on the determining, allocating one of the at least two processor cores to perform at least a portion of operations specified by the child instruction group of the sequence according to the aggregated confidence rating; and
responsive to the allocating, initiating execution of the child instruction group prior to initiating execution of the at least one of the parent instruction groups.

12. The method of claim 11 , wherein the aggregated confidence rating is based at least in part on branch prediction accuracy for one or more branch instructions of the two or more parent instruction groups.

13. The method of claim 11 , further comprising using one or more performance counters to monitor performance of the one or more processor cores, and wherein the aggregated confidence rating is determined based at least in part on data received from the one or more performance counters.

14. The method of claim 11 , wherein the core scheduler is configured to, based at least in part on the aggregated confidence rating increasing, branch to and execute instructions on a processor core that includes previously-fetched, or previously-fetched and previously-decoded, instruction groups.

15. The method of claim 11 , wherein core scheduler is configured to adjust a number of processor cores, a number of functional resources of processor cores, or a number of processor cores and functional resources of processor cores allocated to executing the sequence of instruction groups based on comparing the aggregated confidence rating to one or more predetermined values.

16. The method of claim 11 , wherein the core scheduler is configured to adjust a number of instruction groups that are prefetched, decoded, or executed based on comparing a confidence rating to one or more predetermined values.

17. The method of claim 11 , wherein at least one of the one or more processor cores is configured to prefetch, decode, or prefetch and decode one or more instruction headers for one or more target instruction groups of a currently executing instruction group.

18. One or more computer-readable storage media storing instructions for causing one or more core schedulers to perform a method, the one or more core schedulers controlling one or more processor cores that are configured to fetch and execute a sequence of instruction groups, each of the one or more processor cores comprising functional resources performing operations specified by the sequence of instruction groups, the method comprising:
allocating processor cores performing at least a portion of operations specified by child instruction groups of the sequence by aggregating confidence ratings for two or more parent instruction group

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Gray Jan S
• Burger Douglas C
• Smith Aaron L

Classifications

• G06F9/3858

  Result writeback, i.e. updating the architectural state or memory · CPC title

• G06F9/3854

  Instruction completion, e.g. retiring, committing or graduating · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3804 Primary

  for branches, e.g. hedging, branch folding · CPC title