Initiating instruction block execution using a register access instruction

Patent metadata

Field	Value
Publication number	US-10678544-B2
Application number	US-201615044040-A
Country	US
Kind code	B2
Filing date	Feb 15, 2016
Priority date	Sep 19, 2015
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

Apparatus and methods are disclosed for initiating instruction block execution using a register access instruction (e.g., a register Read instruction). In some examples of the disclosed technology, a block-based computing system can include a plurality of processor cores configured to execute at least one instruction block. The at least one instruction block encodes a data-flow instruction set architecture (ISA). The ISA includes a first plurality of instructions and a second plurality of instructions. One or more of the first plurality of instructions specify at least a first target instruction without specifying a data source operand. One or more of the second plurality of instructions specify at least a second target instruction and a data source operand that specifies a register.

First claim

We claim:

1. A block-based computing system, comprising:
a plurality of processor cores configured to execute at least one instruction block, the at least one instruction block encoding a data-flow instruction set architecture (ISA) comprising:
a Read instruction specifying a target instruction and a data source operand that specifies a register and wherein a result from executing the Read instruction is forwarded to an operand buffer accessed by the target instruction prior to fetching the target instruction; and
the target instruction, which does not specify the register as a data source operand.

2. The block-based computing system of claim 1 , wherein one or more of the plurality of processor cores comprise a register file, and the data source operand points to the register file.

3. The block-based computing system of claim 1 , wherein one or more of the plurality of processor cores is configured to execute the Read instruction prior to completion of fetching the at least one instruction block.

4. The block-based computing system of claim 1 , wherein the Read instruction is an initial instruction of the at least one instruction block.

5. The block-based computing system of claim 1 , wherein one or more instructions in the instruction block specify a pointer to the target instruction.

6. The block-based computing system of claim 1 , wherein the data-flow ISA comprises a predicated instruction associated with a condition.

7. The block-based computing system of claim 6 , wherein one or more other instructions in the instruction block comprise a register Read instruction, and wherein execution of the register Read instruction is predicated upon whether the condition is satisfied.

8. A method of operating a processor to execute an instruction block, the instruction block comprising an instruction block header and a plurality of instructions, the method comprising:
detecting at least one register access instruction during instruction execution, the at least one register access instruction specifying a target instruction and a data source operand;
accessing a register of the processor, the register associated with the data source operand;
retrieving data from the register; and
forwarding the data to an operand buffer of the target instruction, wherein the data is forwarded to the operand buffer of the target instruction prior to fetching the target instruction.

9. The method according to claim 8 , wherein the target instruction is decoded subsequent to the at least one register access instruction.

10. The method according to claim 8 , wherein the at least one register access instruction is a register Read instruction predicated upon satisfaction of a condition associated with a predicated instruction.

11. The method according to claim 8 , wherein the at least one register access instruction is a register Read instruction.

12. The method according to claim 8 , further comprising:
initiating execution of one or more instructions dependent upon the at least one register access instruction, upon decoding the at least one register access instruction.

13. The method according to claim 8 , wherein the at least one register access instruction is executed prior to completion of fetching the plurality of instructions for the instruction block.

14. The method according to claim 8 , wherein the instruction block comprises a plurality of register Read instructions that are part of only the plurality of instructions and not the instruction block header.

15. One or more computer-readable storage media storing computer-readable instructions that when executed by a block-based processor, cause the processor to perform the method of claim 8 .

16. One or more computer-readable storage media storing computer-readable instructions for an instruction block that when executed by a block-based processor, cause the processor to perform a method, the computer-readable instructions comprising instructions that cause the processor to:
decode a plurality of instructions for the instruction block, the plurality of instructions comprising at least a first register Read instruction that initiates execution of the instruction block;
detect a predicated instruction in the plurality of instructions, the predicated instruction having an associated condition;
execute a second register Read instruction, wherein the second register Read instruction is predicated upon whether the associated condition is satisfied; and
prior to fetching a subsequent target instruction, forward a result from executing the second register Read instruction to an operand buffer of the subsequent target instruction.

17. The computer-readable storage media of claim 16 , wherein the computer-readable instructions further cause the processor to:
execute a third register Read instruction for reading a value from a register, wherein a target operand of the third register Read instruction is a broadcast of the value read from the register.

18. The block-based computing system of claim 1 , wherein execution of the Read instruction is predicated on a condition generated by another instruction in the at least one instruction block.

19. The method according to claim 8 , wherein execution of the register access instruction is predicated on a condition generated by another instruction in the plurality of instructions.

20. The method according to claim 8 , further comprising:
subsequent to executing the target instruction, refreshing the instruction block; and
re-executing the instruction block without re-fetching or re-decoding the instruction block.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Burger Douglas C
• Smith Aaron L

Classifications

• G06F9/3822

  Parallel decoding, e.g. parallel decode units · CPC title

• G06F9/345

  of multiple operands or results {(addressing multiple banks G06F12/06)} · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F11/36

  Prevention of errors by analysis, debugging or testing of software · CPC title

• G06F9/30072

  to perform conditional operations, e.g. using predicates or guards · CPC title