Multi-nullification

Patent metadata

Field	Value
Publication number	US-10031756-B2
Application number	US-201615060445-A
Country	US
Kind code	B2
Filing date	Mar 3, 2016
Priority date	Sep 19, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

First claim

We claim:

1. An apparatus comprising a block-based processor, the block-based processor comprising:
one or more processing cores; and
a control unit configured, based at least in part on receiving a nullification instruction, to cause the cores to:
obtain a memory instruction identification for a memory access instruction of a plurality of memory access instructions indicated by a first target field of the nullification instruction, the memory access instruction being encoded as a different instruction in a first instruction block than the nullification instruction;
obtain a register identification of at least one of a plurality of registers, based on a second target field of the nullification instruction;
nullify the memory access instruction associated with the memory instruction identification;
nullify at least one register read associated with the register identification, wherein the at least one register read is in a second instruction block of a plurality of instruction blocks; and
based on the nullified memory access instruction and the nullified at least one register, execute a subsequent memory instruction from the first instruction block, a subsequent register instruction from the second instruction block, or a subsequent memory instruction from the first instruction block and a subsequent register instruction from the second instruction block.

2. The apparatus of claim 1 , wherein the control unit is configured to nullify the at least one register and the memory access instruction by fetching and executing the nullification instruction encoded in the first instruction block.

3. The apparatus of claim 1 , further comprising:
a hardware structure configured to store:
data indicating execution ordering of the plurality of memory access instructions, wherein the data indicating execution ordering is a store mask based at least in part on a plurality of load/store identifiers (LSIDs) encoded for the plurality of memory access instructions in the first instruction block; and
data indicating one or more of the plurality of registers that data will be written to during execution of the first instruction block.

4. The apparatus of claim 3 , wherein the memory access instruction is a memory store instruction, and the memory instruction identification comprises an LSID from the plurality of LSIDs, for the memory store instruction.

5. The apparatus of claim 1 , wherein the memory instruction identification is an LSID, and the control unit is further configured, during the nullifying, to:
mark the LSID of the memory access instruction as completed, as if the memory access instruction has executed; and
mark at least one register writing instruction writing to the at least one register as completed, as if the at least one register writing instruction has executed.

6. The apparatus of claim 1 , further comprising an instruction decoder configured to:
decode the plurality of memory access instructions and register writing instructions of the first instruction block; and
detect at least one predicated instruction, the predicated instruction being associated with a first predicated execution path and a second predicated execution path.

7. The apparatus of claim 6 , wherein the control unit is further configured to, during execution of instructions in the first predicated execution path:
detect in the second predicated execution path, a memory store instruction and an instruction writing to at least a second register of the plurality of registers; and
nullify the memory store instruction and the at least second register, while executing the instructions in the first predicated execution path, as if the memory store instruction and the instruction writing to the at least second register have executed.

8. The apparatus of claim 7 , wherein the nullifying of the memory store instruction and the at least second register while executing the instructions in the first predicated execution path takes place without inserting a separate nullification instruction in the first instruction block.

9. The apparatus of claim 1 , wherein the control unit is configured to nullify the memory access instruction by increasing a first instruction count of store instructions that have been executed within the first instruction block.

10. The apparatus of claim 9 , wherein the control unit is configured to nullify the at least one register by increasing a second instruction count of register write instructions writing to one or more of the plurality of registers and that have been executed within the first instruction block.

11. The apparatus of claim 10 , wherein the control unit is configured to execute the subsequent memory access instruction when the first instruction count and the second instruction count reach a pre-determined value.

12. The apparatus of claim 1 , wherein the control unit is further configured to:
based on the nullified memory access instruction and the nullified at least one register, commit the first instruction block and execute at least one instruction from at least a second instruction block of the plurality of instruction blocks.

13. A method of operating a processor to execute a block of instructions comprising a plurality of memory store instructions and a plurality of register writing instructions, the method comprising:
retrieving data indicating execution ordering of the plurality of memory store instructions;
retrieving data indicating one or more of a plurality of registers that the plurality of register writing instructions will write to;
detecting a predicated memory instruction during instruction execution;
determining at least a first memory store instruction of the plurality of memory store instructions and at least a first register writing instruction of the plurality of register writing instructions that will not execute when a condition of the predicated instruction is satisfied;
generating a nullification instruction, wherein a first target field of the nullification instruction identifies a load/store identifier (LSID) of the first memory store instruction, and a second target field of the nullification instruction identifies a register number of at least one of the plurality of registers the at least first register writing instruction writes to; and
issuing the predicated instruction.

14. The method according to claim 13 , wherein the first target field comprises a first mask and a first shift bit, the LSID of the first memory store instruction being identified based on the first mask and the first shift bit.

15. The method according to claim 14 , wherein the second target field comprises a second mask and a second shift bit, the at least first register writing instruction being identified based on the second mask and the second shift bit.

16. The method according to claim 13 , further comprising:
analyzing memory accesses encoded in source code and/or object code to determine memory dependencies for the block of instructions; and
transforming the source code and/or object code into computer-executable code for the instruction block, the computer-executable code including memory access instructions and register writing instructions that can be used to generate the nullification instructions.

17. The method according to claim 16 , further comprising:
storing the one or more nullification instructions in the block of instructions, the nullification instruction comprising a first target field identifying a load/store identifier of at least one of the memory access instructions, and a second target field identifying at least one of a plur

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Burger Douglas C
• Smith Aaron L

Classifications

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F15/8007

  single instruction multiple data [SIMD] multiprocessors · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/3848

  using hybrid branch prediction, e.g. selection between prediction techniques · CPC title

• G06F9/30072

  to perform conditional operations, e.g. using predicates or guards · CPC title