Hybrid block-based processor and custom function blocks

Patent metadata

Field	Value
Publication number	US-11449342-B2
Application number	US-201615224624-A
Country	US
Kind code	B2
Filing date	Jul 31, 2016
Priority date	Apr 28, 2016
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

Apparatus and methods are disclosed for implementing block-based processors having custom function blocks, including field-programmable gate array (FPGA) implementations. In some examples of the disclosed technology, a dynamically configurable scheduler is configured to issue at least one block-based processor instruction. A custom function block is configured to receive input operands for the instruction and generate ready state data indicating completion of a computation performed for the instruction by the respective custom function block.

First claim

We claim:

1. A method of operating a configurable logic device to execute a block-based processor instruction set, the method comprising:
initiating execution of an instruction block containing a plurality of instructions encoded according to the block-based processor instruction set; and
executing one of the instructions, the executed instruction specifying use of a custom function block implemented with the configurable logic device, the configurable logic device including an operand buffer to store instruction operands, by:
issuing a first instruction of a set of two or more fused instructions, the first instruction specifying use of the custom function block and producing at least one result operand, and
responsive to data encoded in the first instruction or a second instruction, the data being encoded in a field exclusively used to indicate the second instruction is fused to the first instruction, issuing the second instruction of the set of two or more fused instructions to the custom function block after the first instruction executes, the second instruction being issued in a sequence so that the custom function block executing the second instruction will receive the at least one result operand by bypassing an operand buffer.

2. The method of claim 1 , wherein a function performed by the custom function block is defined at least in part based on a parameter.

3. The method of claim 2 , wherein the parameter is defined by an operand of the executing instruction.

4. The method of claim 1 , wherein the custom function block comprises programmable logic devices of the configurable logic device, the method further comprising:
configuring the programmable logic devices to implement the custom function block.

5. The method of claim 1 , further comprising:
executing one or more instruction blocks with general-purpose execution units of the block-based processor;
based on performance data for the instruction blocks generated by a profiler, configuring the custom function block to perform a function; and
executing the instructions block with the configured custom function block.

6. A method of operating a reconfigurable logic device configured to execute an instruction set and having an operand buffer for temporarily storing instruction operands, the method comprising:
receiving a first instruction having a first field exclusively used to indicate that the instruction is fused with a second instruction and having a second field indicating that the instruction is to be executed with a custom function block, and responsive to decoding the first field and the second field:
issuing the first instruction for execution using the custom function block implemented with the reconfigurable logic device, producing at least one result operand; and
issuing the second instruction to the custom function block for execution, the second instruction being issued in a sequence so that the custom function block executing the second instruction will receive the at least one result operand by bypassing an operand buffer.

7. The method of claim 6 , further comprising, based on the first field, executing the first instruction immediately before the second instruction.

8. The method of claim 6 , further comprising delaying the issuing the first instruction, despite all dependencies of the first instruction being satisfied, until all dependencies of the second instruction are satisfied.

9. The method of claim 6 , further comprising delaying the issuing the first instruction and the issuing the second instruction until all source operands for the first instruction and the second instruction are available.

10. The method of claim 6 , further comprising:
executing the second instruction immediately after the first instruction, wherein at least one of the second instruction's source operands is generated by the first instruction.

11. An apparatus comprising:
a decoder to decode a set of two or more instructions and designate the set of instructions as fused when indicated by an opcode or another instruction in a group of instructions;
a customizable function unit situated to perform operations specified by the fused set of two or more instructions;
an operand buffer situated to temporarily store output operands produced by executing instructions with the customizable function unit and to output operands via a number of read ports; and
an instruction scheduler configured to issue the fused set of instructions in a manner allowing bypass of the operand buffer, at least one of the fused set of instructions receiving a result produced by the executing instructions by bypassing an operand buffer.

12. The apparatus of claim 11 , wherein the instruction scheduler is further configured to, based on a field encoded in a first one of the fused set of instructions, execute the first instruction immediately before the second instruction, thereby allowing bypass of the operand buffer.

13. The apparatus of claim 11 , wherein the instruction scheduler is further configured to, based on the indication that the set of instructions is fused, delay issuing of a first instruction of the set of fused instructions until all dependencies of a second instruction of the set of fused instructions is satisfied.

14. The apparatus of claim 11 , wherein:
the set of fused instructions comprises a first instruction and a second instruction; and
the instruction scheduler is further configured to, based on the indication that the set of instructions is fused, execute the second instruction immediately after the first instruction, wherein at least one of the second instruction's source operands are generated by the first instruction.

15. The apparatus of claim 11 , wherein the instruction scheduler is further configured to:
issue at least two of the fused instructions simultaneously, wherein the number of operands consumed by the simultaneously-issued fused instructions is greater than the number of read ports of the operand buffer.

16. The apparatus of claim 11 , wherein the opcode comprises data indicating which instructions in a stream of instructions are fused.

17. A method comprising:
producing a configuration bitstream comprising configuration data for implementing a processor with a reconfigurable logic device, the processor comprising:
a decoder to decode a set of two or more instructions and designate the set of instructions as fused when indicated by an opcode or another instruction in a group of instructions;
a customizable function unit situated to perform operations specified by the fused set of two or more instructions;
an operand buffer situated to temporarily store output operands produced by executing instructions with the customizable function unit; and
an instruction scheduler configured to issue the fused set of instructions in a manner that, when a first instruction of the fused set of instructions produces at least one result operand, the customizable function unit will receive the at least one result operand by bypassing the operand buffer.

18. The method of claim 17 , wherein the instruction scheduler issues at least two of the fused instructions simultaneously.

19. The method of claim 18 , wherein the number of operands consumed by the simultaneously-issued instructions is greater than the number of read ports of the operand buffer.

20. The method of claim 17 , further comprising:
storing the configuration bitstream in a computer-readable storage device or memory.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Smith Aaron L
• Gray Jan S

Classifications

• G06F9/3889

  controlled by multiple instructions, e.g. MIMD, decoupled access or execute · CPC title

• G06F9/3897

  with adaptable data path · CPC title

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title