Multimodal targets in a block-based processor

Patent metadata

Field	Value
Publication number	US-10445097-B2
Application number	US-201615073365-A
Country	US
Kind code	B2
Filing date	Mar 17, 2016
Priority date	Sep 19, 2015
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Apparatus and methods are disclosed for decoding targets from an instruction and transmitting data to those targets in accordance with a current instruction. Multimodal target hardware is used in conjunction with one or more of the routers so as to route data to an appropriate target. The data can be one or more operands or a predicate and the targets can include operand buffers, broadcast channels, and general registers. In this way, operands, for example, can be directed for use with multiple subsequent instructions, and there are multiple modes for distributing the operands to the multiple instructions.

First claim

We claim:

1. An apparatus comprising multiple block-based processor cores, at least one of the processor cores comprising:
one or more routers configured to route data associated with instructions within a plurality of instructions to one or more other instructions; and
a control unit coupled to the one or more routers and configured to cause the processor core to execute a current instruction within the plurality of instructions and to decode a target field from the current instruction and control bits in the current instruction, the control unit further configured to control the one or more routers to route data associated with the current instruction to any of three or more different target types in accordance with the target field, wherein the control bits in the current instruction are used to identify the three or more different target types;
wherein at least one of the three or more different target types identified by the control bits is a broadcast channel internal within the processor core that allows writing the data from the current instruction to operands of two or more subsequent instructions, in parallel, to be used as an operand of the two or more subsequent instructions of the plurality of instructions within the processor core.

2. The apparatus of claim 1 , wherein at least one of the three or more different target types is a general purpose register within the at least one processor core and the data is an operand associated with the current instruction.

3. The apparatus of claim 1 , wherein the three or more different target types include an operand buffer, a general purpose register and a broadcast channel.

4. The apparatus of claim 1 , wherein the control unit is configured to interpret control bits within the target field, the control bits indicating how to interpret a remainder of the target field.

5. The apparatus of claim 4 , wherein the interpreting includes using at least a portion of the remainder of the target field as extended control bits.

6. The apparatus of claim 1 , wherein the target field includes an identifier of one of the three or more different target types.

7. The apparatus of claim 1 , wherein the control unit includes a decoder that is configured to receive input bits from the target field and to generate control signals to the one or more routers based on the input bits.

8. The apparatus of claim 7 , wherein the one or more routers are configured to be responsive to the control signals to switch the data from the current instruction to any of the three or more different targets.

9. The apparatus of claim 1 , wherein the current instruction includes an opcode that is separate from the target field.

10. A method, comprising:
in a first processor core of a block-based processor, which includes multiple processor cores interconnected through a core interconnect to the first processor core:
inputting, into a control unit within the first processor core, a target field of a current instruction, the target field identifying any one of at least three candidate target types to which data associated with the current instruction is to be transmitted;
decoding control bits within the target field in order to identify which of the three candidate target types is to receive the data, wherein one of the three candidate target types is a broadcast channel and another of the three candidate target types is a register; and
transmitting control signals from the control unit to one or more routers that receive the data and route the data based at least in part on the identified target type;
wherein the data is routed, by the one or more routers, to the broadcast channel internal within the first processor core that transmits the data to more than one instruction for use as an operand of the more than one instruction within a single instruction window to be executed within the first processor core.

11. The method of claim 10 , further including interpreting, within the control unit, a remainder of the target field based on the control bits, wherein bits of the target field are interpreted as extended control bits or as at least part of an identifier based on the control bits.

12. The method of claim 10 , wherein the one or more routers include switching logic to transmit the data, based at least in part on the identified target type, in response to the control signals.

13. The method of claim 10 , wherein the control unit includes multimodal target hardware including a decoder for performing the decoding.

14. The method of claim 10 , wherein the data is an operand to be used by other instructions within the first processor core.

15. One or more computer readable storage media, which are nonvolatile storage, for storing computer-readable instructions that when executed by a block-based processor cause the block-based processor to perform a method, the method comprising:
in a current instruction of a processor core within the block-based processor, receiving an opcode field and a target field, the target field indicating where a result of the current instruction is to be sent;
decoding the target field and determining a broadcast identifier indicating a broadcast channel within the processor core to be used to transmit the result to multiple instructions in the processor core, wherein the target field includes control bits that identify a target type is the broadcast channel and wherein the control bits identify any one of three different target types where the result is to be sent;
routing the result to the broadcast channel using control signals generated as a result of the decoding; and
inserting the result into multiple instructions in a single instruction window.

16. The one or more computer readable storage media of claim 15 , wherein the three candidate target types include at least the broadcast channel, one or more operand buffers, and a general register file.

17. The one or more computer readable storage media of claim 15 , wherein the receiving instruction includes an indication of the broadcast channel to receive target data.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Burger Douglas C
• Smith Aaron L

Classifications

• G06F9/3828

  with global bypass, e.g. between pipelines, between clusters · CPC title

• G06F9/30138

  Extension of register space, e.g. register cache · CPC title

• G06F15/8007

  single instruction multiple data [SIMD] multiprocessors · CPC title

• G06F11/3656

  using a specific debug interface · CPC title

• G06F9/355

  Indexed addressing · CPC title