Debug support for block-based processor

Patent metadata

Field	Value
Publication number	US-10776115-B2
Application number	US-201514942557-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Sep 19, 2015
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Systems and methods are disclosed for supporting debugging of programs in block-based processor architectures. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising an instruction header and a plurality of instructions. The block-based processor core includes execution control logic and core state access logic. The execution control logic can be configured to schedule respective instructions of the plurality of instructions for execution in a dynamic order during a default execution mode and to schedule the respective instructions for execution in a static order during a debug mode. The core state access logic can be configured to read intermediate states of the block-based processor core and to provide the intermediate states outside of the block-based processor core during the debug mode.

First claim

We claim:

1. A processor comprising:
a plurality of block-based processor cores including a first block-based processor core for executing an instruction block comprising an instruction header and a plurality of instructions, the first block-based processor core comprising:
execution control logic configured to schedule respective instructions of the plurality of instructions for execution in a dynamic order during a default execution mode and to schedule the respective instructions for execution in a static order during a debug mode, the dynamic order determined during execution of the instruction block and based on when operands of the plurality of the instructions are ready, the static order determined based on information that is available before the instruction block is executed;
core state access logic in communication with the execution control logic, the core state access logic configured to read intermediate states of the block-based processor core and to provide the intermediate states outside of the block-based processor core only during the debug mode; and

a hardware control unit comprising a debug control module coupled to the plurality of block-based processor cores, the debug control module configured to receive the intermediate states from the core state access logic and to update at least one of the intermediate states based on input from a user.

2. The processor of claim 1 , wherein the static order is a compiler-generated order.

3. The processor of claim 1 , wherein the static order is based on a breadth-first traversal of a dependence graph of the instruction block.

4. The processor of claim 1 , wherein the static order is different than a compiler-generated order, and wherein the execution control logic is further configured to receive information indicating which instruction of the instruction block to execute.

5. The processor of claim 1 , wherein the intermediate states of the processor core comprise operand buffers of an instruction window of the processor core.

6. The processor of claim 1 , further comprising:
header decode logic in communication with the execution control logic, the header decode logic configured to decode the instruction header of the instruction block, and wherein the debug mode is initiated in response to decoding an asserted flag of the instruction header.

7. The processor of claim 1 , wherein the intermediate states of the block-based processor core are uncommitted results that are local to the block-based processor core.

8. A method of executing a first instruction block, comprising a first instruction block header and a first plurality of instructions, on a first block-based processor core, and executing a second instruction block, comprising a second instruction block header and a second plurality of instructions, on a second block-based processor core, the method comprising:
scheduling the first plurality of instructions for execution in a dynamic order during a default execution mode, the dynamic order determined during execution of the first instruction block and based on when operands of the first plurality of the instructions are ready;
determining, by a debug control module of a hardware control unit shared between the first and second block-based processor cores and based on information that is available before the second instruction block is executed, a static order for execution of the second plurality of instructions, the static order differing from a compiler-generated order for execution of the second plurality of instructions;
scheduling the plurality of instructions of the second instruction block for execution in the static order during a debug mode;
reading intermediate states of the second block-based processor core; and
providing the intermediate states outside of the second block-based processor core to the debug control module.

9. The method of claim 8 , wherein the static order is based on a breadth-first traversal of a dependence graph of the second instruction block.

10. The method of claim 8 , wherein the method further comprises:
receiving, at the second block-based processor core, from the debug control module, information indicating which instruction of the second instruction block to execute.

11. The method of claim 8 , wherein the intermediate states of the processor core comprise operand buffers of an instruction window of the second block-based processor core.

12. The method of claim 8 , further comprising:
decoding the second instruction block header, and
initiating the debug mode in response to decoding an asserted flag of the second instruction block header.

13. The method of claim 8 , wherein the intermediate states of the second block-based processor core are uncommitted results that are local to the second block-based processor core.

14. One or more computer-readable non-volatile storage devices or memory components storing computer-readable instructions that when executed by an apparatus comprising a block-based processor core, cause the apparatus to perform a method, the computer-readable instructions comprising:
first instructions to receive an instruction block comprising an instruction header and a plurality of program instructions;
second instructions to schedule the plurality of program instructions for execution in a dynamic order during a default execution mode, the dynamic order determined during execution of the instruction block and based on when operands of the plurality of program instructions are ready;
third instructions to schedule the plurality of program instructions for execution in a static order during a debug mode, the static order determined based on information that is available before the instruction block is executed;
fourth instructions to read intermediate states of the block-based processor core; and
fifth instructions to provide the intermediate states outside of the block-based processor core, to a debug control module of a hardware control unit shared between the block-based processor core and another block-based processor core, only during the debug mode, wherein the intermediate states are not visible to the another block-based processor core.

15. The one or more computer-readable non-volatile storage devices or memory components of claim 14 , wherein the static order is a compiler-generated order.

16. The one or more computer-readable non-volatile storage devices or memory components of claim 14 , wherein the static order is based on a breadth-first traversal of a dependence graph of the instruction block.

17. The one or more computer-readable non-volatile storage devices or memory components of claim 14 , wherein the static order is different than a compiler-generated order for execution of the plurality of program instructions, and wherein the computer-readable instructions further comprise:
sixth instructions to receive information indicating which program instruction of the instruction block to execute.

18. The one or more computer-readable non-volatile storage devices or memory components of claim 14 , wherein the intermediate states of the block-based processor core comprise operand buffers of an instruction window of the block-based processor core.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Burger Douglas C
• Smith Aaron L

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/30058

  Conditional branch instructions · CPC title

• G06F9/3005

  to perform operations for flow control · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3858

  Result writeback, i.e. updating the architectural state or memory · CPC title