Z-Dimension Cache Layer Pipelining
US-2026003806-A1 · Jan 1, 2026 · US
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Moyer Paul James patents
Moyer Paul James is listed as an inventor on 40 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Moyer Paul James |
| Total patents | 40 |
| First publication | Dec 14, 2017 |
| Latest publication | Jan 1, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Super-temporal cache replacement policy
US-12455823-B2 · Oct 28, 2025 · US
Stacked Die Extension Over Processor Core
US-2025307143-A1 · Oct 2, 2025 · US
Cache Data Distribution for a Stacked Die Configuration
US-2025307162-A1 · Oct 2, 2025 · US
Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches
US-12306754-B2 · May 20, 2025 · US
System probe aware last level cache insertion bypassing
US-12204454-B2 · Jan 21, 2025 · US
Super-Temporal Cache Replacement Policy
US-2024411692-A1 · Dec 12, 2024 · US
Throttling while managing upstream resources
US-12032965-B2 · Jul 9, 2024 · US
System and method for storing cache location information for cache entry transfer
US-12026099-B2 · Jul 2, 2024 · US
Method and Apparatus for Increasing Memory Level Parallelism by Reducing Miss Status Holding Register Allocation in Caches
US-2024202116-A1 · Jun 20, 2024 · US
Recent patents
Latest publications not already listed above.
Quality of service dirty line tracking
US-11669457-B2 · Jun 6, 2023 · US
Oldest operation wait time indication input into set-dueling
US-11561895-B2 · Jan 24, 2023 · US
Probe interrupt delivery
US-2022100686-A1 · Mar 31, 2022 · US
Throttling while managing upstream resources
US-2022058025-A1 · Feb 24, 2022 · US
System probe aware last level cache insertion bypassing
US-2022050785-A1 · Feb 17, 2022 · US
Probe interrupt delivery
US-11210246-B2 · Dec 28, 2021 · US
Quality of service dirty line tracking
US-2021390057-A1 · Dec 16, 2021 · US
Throttling while managing upstream resources
US-11169812-B2 · Nov 9, 2021 · US
System probe aware last level cache insertion bypassing
US-11163688-B2 · Nov 2, 2021 · US
Quality of service dirty line tracking
US-11106594-B2 · Aug 31, 2021 · US
System and method for storing cache location information for cache entry transfer
US-2021173789-A1 · Jun 10, 2021 · US
Throttling while managing upstream resources
US-2021096873-A1 · Apr 1, 2021 · US
System probe aware last level cache insertion bypassing
US-2021089462-A1 · Mar 25, 2021 · US
System and method for storing cache location information for cache entry transfer
US-10956339-B2 · Mar 23, 2021 · US
Quality of service dirty line tracking
US-2021073137-A1 · Mar 11, 2021 · US
Oldest operation wait time indication input into set-dueling
US-2021073126-A1 · Mar 11, 2021 · US
System and method for identifying pendency of a memory access request at a cache entry
US-10922230-B2 · Feb 16, 2021 · US
Probe interrupt delivery
US-2020065275-A1 · Feb 27, 2020 · US
Scaled set dueling for cache replacement policies
US-10430349-B2 · Oct 1, 2019 · US
Scheduling independent and dependent operations for processing
US-10339063-B2 · Jul 2, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Advanced Micro Devices Inc | 40 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0811 | 24 |
| G06F12/0897 | 15 |
| Y02D10/00 | 12 |
| G06F2212/1016 | 12 |
| G06F12/126 | 11 |