Quality of service dirty line tracking

Patent metadata

Field	Value
Publication number	US-11669457-B2
Application number	US-202117459100-A
Country	US
Kind code	B2
Filing date	Aug 27, 2021
Priority date	Sep 5, 2019
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.

First claim

What is claimed is:

1. A cache control unit comprising:
circuitry configured to:
detect one or more writes to cache lines stored in a cache; and
generate a measurement of memory bandwidth based at least in part on a determination that one or more of the writes are to unmodified cache lines.

2. The cache control unit as recited in claim 1 , wherein the circuitry is configured to:
maintain a counter to track writes to unmodified cache lines stored in the cache; and
generate the measurement of memory bandwidth based at least in part on the counter.

3. The cache control unit as recited in claim 2 , wherein the circuitry is configured to:
determine a difference between a value of the counter at a first point in time and a value of the counter at a second point in time; and
determine the measurement of memory bandwidth based at least in part on the difference.

4. The cache control unit as recited in claim 2 , wherein the circuitry is configured to increment the counter responsive to a determination that a given write operation to a first cache line is a first modification of the first cache line since the first cache line entered the cache.

5. The cache control unit as recited in claim 4 , wherein the circuitry configured to maintain a value of the counter responsive to a determination that the given write to the first cache line is not the first modification of the first cache line since the first cache line entered the cache.

6. The cache control unit as recited in claim 3 , wherein the circuitry is configured to determine a number of clock cycles that elapsed between the first point in time and the second point in time.

7. The cache control unit as recited in claim 1 , wherein the circuitry is configured to add the measurement of memory bandwidth to a measurement of read memory bandwidth to determine a total memory bandwidth.

8. A method comprising:
detecting one or more writes to cache lines stored in a cache; and
generating a measurement of memory bandwidth based at least in part on a determination that one or more of the writes are to unmodified cache lines.

9. The method as recited in claim 8 , further comprising:
maintaining a counter to track writes to unmodified cache lines stored in the cache; and
generating the measurement of memory bandwidth based at least in part on the counter.

10. The method as recited in claim 9 , further comprising
determining a difference between a value of the counter at a first point in time and a value of the counter at a second point in time; and
determining the measurement of memory bandwidth based at least in part on the difference.

11. The method as recited in claim 9 , comprising incrementing the counter responsive to a determination that a given write operation to a first cache line is a first modification of the first cache line since the first cache line entered the cache.

12. The method as recited in claim 11 , further comprising maintaining a value of the counter responsive to determining that the given write to the first cache line is not the first modification of the first cache line since the first cache line entered the cache.

13. The method as recited in claim 10 , further comprising determining a number of clock cycles that elapsed between the first point in time and the second point in time.

14. A system comprising:
a memory subsystem; and
a processor coupled to the memory subsystem;
wherein the processor is configured to:
detect one or more writes to cache lines stored in a cache; and
generate a measurement of memory bandwidth based at least in part on a determination that one or more of the writes are to unmodified cache lines.

15. The system as recited in claim 14 , wherein the processor is configured to:
maintain a counter to track writes to unmodified cache lines stored in the cache; and
generate the measurement of memory bandwidth based at least in part on the counter.

16. The system as recited in claim 15 , wherein the processor is configured to:
determine a difference between a value of the counter at a first point in time and a value of the counter at a second point in time; and
determine the measurement of memory bandwidth based at least in part on the difference.

17. The system as recited in claim 15 , wherein the processor is configured to increment the counter responsive to a determination that a given write operation to a first cache line is a first modification of the first cache line since the first cache line entered the cache.

18. The system as recited in claim 17 , wherein the processor is configured to maintain a value of the counter responsive to a determination that the given write to the first cache line is not the first modification of the first cache line since the first cache line entered the cache.

19. The system as recited in claim 16 , wherein the processor is configured to determine a number of clock cycles that elapsed between the first point in time and the second point in time.

20. The system as recited in claim 14 , wherein the processor is configured to add the measurement of memory bandwidth to a measurement of read memory bandwidth to calculate a total memory bandwidth.

Assignees

• Advanced Micro Devices Inc

Inventors

• Moyer Paul James
• Hunt Douglas Benson

Classifications

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F9/3816

  Instruction alignment, e.g. cache line crossing · CPC title

• G06F12/0891 Primary

  using clearing, invalidating or resetting means · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/126 Primary

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title