Throttling while managing upstream resources

Patent metadata

Field	Value
Publication number	US-12032965-B2
Application number	US-202117519902-A
Country	US
Kind code	B2
Filing date	Nov 5, 2021
Priority date	Sep 26, 2019
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

Systems, apparatuses, and methods for arbitrating threads in a computing system are disclosed. A computing system includes a processor with multiple cores, each capable of simultaneously processing instructions of multiple threads. When a thread throttling unit receives an indication that a shared cache has resource contention, the throttling unit sets a threshold number of cache misses for the cache. If the number of cache misses exceeds this threshold, then the throttling unit notifies a particular upstream computation unit to throttle the processing of instructions for the thread. After a time period elapses, if the cache continues to exceed the threshold, then the throttling unit notifies the upstream computation unit to more restrictively throttle the thread by performing one or more of reducing the selection rate and increasing the time period. Otherwise, the unit notifies the upstream computation unit to less restrictively throttle the thread.

First claim

What is claimed is:

1. A processor comprising:
control circuitry configured to:
compare a number of cache misses of a given thread, during execution of a plurality of threads including the given thread, to a threshold; and
cause a number of instructions of the given thread to be throttled, in response to the number of cache misses of the given thread exceeding the threshold.

2. The processor as recited in claim 1 , wherein the control circuitry is configured to cause the given thread to be throttled for a given period of time.

3. The processor as recited in claim 1 , wherein responsive to elapse of a given period of time, the control circuitry is configured to determine whether a number of cache misses of the given thread during the given period of time exceeds the threshold.

4. The processor as recited in claim 3 , wherein responsive to determining cache misses of the given thread exceed the threshold, subsequent to elapse of the given period of time, the control circuitry is configured to cause the given thread to be throttled with a more restrictive level, such that a number of instructions processed by the given thread is reduced.

5. The processor as recited in claim 3 , wherein responsive to determining cache misses of the given thread do not exceed the threshold, subsequent to elapse of the given period of time, the control circuitry is configured to cause the given thread to be throttled with a less restrictive level, such that a number of instructions processed by the given thread is increased.

6. The processor as recited in claim 1 , wherein the control circuitry is configured to store data that identifies a thread that is throttled.

7. The processor as recited in claim 6 , wherein the data further comprises one or more of the threshold, a throttling severity level, a selection rate and a time period.

8. The processor as recited in claim 1 , wherein the control circuitry is configured to identify the number of cache misses as corresponding to the given thread.

9. A method comprising:
comparing a number of cache misses of a given thread, during execution of a plurality of threads including the given thread, to a threshold; and
causing a number of instructions of the given thread to be throttled, in response to the number of cache misses of the given thread exceeding the threshold.

10. The method as recited in claim 9 , further comprising causing the given thread to be throttled for a given period of time.

11. The method as recited in claim 9 , wherein responsive to elapse of a given period of time, the method comprises determining whether a number of cache misses of the given thread during the given period of time exceeds the threshold.

12. The method as recited in claim 11 , wherein responsive to determining cache misses of the given thread exceed the threshold, subsequent to elapse of the given period of time, the method comprises causing the given thread to be throttled with a more restrictive level, such that a number of instructions processed by the given thread is reduced.

13. The method as recited in claim 11 , wherein responsive to determining cache misses of the given thread do not exceed the threshold, subsequent to elapse of the given period of time, the method comprises causing the given thread to be throttled with a less restrictive level, such that a number of instructions processed by the given thread is increased.

14. The method as recited in claim 9 , further comprising storing data that identifies a thread that is throttled.

15. The method as recited in claim 14 , wherein the data further comprises one or more of the threshold, a throttling severity level, a selection rate and a time period.

16. The method as recited in claim 9 , further comprising identifying the number of cache misses as corresponding to the given thread.

17. A system comprising:
a plurality of computation units; and
a thread throttling unit configured to:
identify a given thread as a candidate for throttling, during execution of a plurality of threads including the given thread, based at least in part on resource usage by the given thread; and
cause a number of instructions of the given thread to be throttled, in response to the given thread having been identified as a candidate for throttling and a number of cache misses of the thread exceeding a threshold.

18. The system as recited in claim 17 , wherein the resource usage corresponds to a cache shared by the plurality of computation units.

19. The system as recited in claim 18 , wherein the thread throttling unit is configured to cause the given thread to be throttled responsive to a number of cache misses exceeding a threshold.

20. The system as recited in claim 17 , wherein the resource usage corresponds to at least one of an instruction fetch unit, a branch prediction unit, a reservation station, a load queue, store queue, and a data bus.

Assignees

• Advanced Micro Devices Inc

Inventors

• Moyer Paul James
• Hunt Douglas Benson
• Troester Kai

Classifications

• G06F9/3851 Primary

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F9/384

  Register renaming · CPC title

• G06F9/3856 Primary

  Reordering of instructions, e.g. using queues or age tags · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title