System and method for storing cache location information for cache entry transfer

Patent metadata

Field	Value
Publication number	US-10956339-B2
Application number	US-201615210846-A
Country	US
Kind code	B2
Filing date	Jul 14, 2016
Priority date	Jul 14, 2016
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

A cache stores, along with data that is being transferred from a higher level cache to a lower level cache, information indicating the higher level cache location from which the data was transferred. Upon receiving a request for data that is stored at the location in the higher level cache, a cache controller stores the higher level cache location information in a status tag of the data. The cache controller then transfers the data with the status tag indicating the higher level cache location to a lower level cache. When the data is subsequently updated or evicted from the lower level cache, the cache controller reads the status tag location information and transfers the data back to the location in the higher level cache from which it was originally transferred.

First claim

What is claimed is:

1. A method, comprising:
in response to a cache miss at a first cache, transferring first data from an entry of a second cache to the first cache;
storing, in the first cache, location information indicating the entry of the second cache in a portion of bits of the first data; and
in response to receiving updated data at the first cache, transferring the updated data from the first cache to the same entry of the second cache indicated by the stored location information; or
in response to evicting the first data from the first cache, transferring the first data from the first cache to the same entry of the second cache indicated by the stored location information.

2. The method of claim 1 , wherein storing the location information comprises generating a location tag with the location information indicating the entry of the second cache.

3. The method of claim 2 , wherein generating the location tag comprises modifying a status tag indicating a memory coherence status of the first data.

4. The method of claim 2 , further comprising storing the location tag in a location tag buffer.

5. The method of claim 2 , further comprising storing the location tag with the first data at the first cache.

6. The method of claim 1 , further comprising modifying the first data in response to receiving the updated data before transferring the updated data from the first cache to the entry of the second cache.

7. The method of claim 1 , wherein the second cache is inclusive of the first cache.

8. The method of claim 1 , wherein:
storing the location information includes a cache controller storing the location information in a status tag of the bits of the first data;
the location information includes a set and a way of the second cache; and
the second cache is divided into a number of sets, each set including a number of ways, and each way corresponding to a cache entry that stores a cache line.

9. A method, comprising:
in response to a memory access request for first data located in a first cache, generating a location tag indicating an entry of the first cache that stores the first data;
storing the location tag in a portion of bits of the first data;
transferring the first data and the location tag to a second cache;
storing, in the second cache, the location tag with the first data; and
in response to receiving, at the second cache, updated data for the first data, transferring the updated data back to the entry of the first cache indicated by the location tag.

10. The method of claim 9 , wherein generating the location tag comprises modifying a status tag indicating a memory coherence status of the first data.

11. The method of claim 9 , wherein generating the location tag comprises storing an index and way of the entry of the first cache.

12. The method of claim 9 , further comprising storing the location tag in a location tag buffer in response to transferring the first data and the location tag to the second cache.

13. The method of claim 9 , wherein the first cache is inclusive of the second cache.

14. A device, comprising:
a first cache;
a second cache; and
a cache controller, associated with the second cache, the cache controller configured to:
transfer first data from an entry in the second cache to the first cache;
store, in the first cache, location information indicating the entry of the second cache in a portion of bits of the first data; and
in response to receiving updated data at the first cache for the first data, transferring the updated data from the first cache to the entry of the second cache indicated by the stored location information in the portion of bits of the first data.

15. The device of claim 14 , wherein the cache controller is further configured to update the first data in response to receiving the updated data prior to transferring the updated data from the first cache to a set and way in the second cache indicated by the stored location information.

16. The device of claim 14 , wherein the second cache is inclusive of the first cache.

17. The device of claim 14 , wherein the cache controller is configured to store the location information in a location tag buffer.

18. The device of claim 14 , wherein the cache controller is configured to store the location information in a status tag indicating a coherency status of the data.

Assignees

• Advanced Micro Devices Inc

Inventors

• Moyer Paul James

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0895 Primary

  of parts of caches, e.g. directory or tag array · CPC title