Quality of service dirty line tracking

Patent metadata

Field	Value
Publication number	US-2021073137-A1
Application number	US-201916562128-A
Country	US
Kind code	A1
Filing date	Sep 5, 2019
Priority date	Sep 5, 2019
Publication date	Mar 11, 2021
Grant date	—

Abstract

Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.

First claim

What is claimed is:

1 . A processor comprising:
a cache hierarchy; and a control unit configured to:
increment a counter when a cache line is modified for a first time since the cache line entered the cache hierarchy;
generate a measurement of write memory bandwidth based on a value of the counter; and
cause a number of write operations that are conveyed to a memory subsystem to be reduced responsive to the measurement of write memory bandwidth exceeding a given threshold.

2 . The processor as recited in claim 1 , wherein the control unit is further configured to:
detect a write operation targeting a first cache line; and increment the counter responsive to determining that the write operation to the first cache line is a first modification of the first cache line since the first cache line entered the cache hierarchy.

3 . The processor as recited in claim 2 , wherein the control unit is further configured to keep the counter unchanged responsive to determining that the write to the first cache line is not the first modification of the first cache line since the first cache line entered the cache hierarchy.

4 . The processor as recited in claim 1 , wherein the control unit is further configured to:
record a first value of the counter at a first point in time; record a second value of the counter at a second point in time, wherein the second point in time is subsequent to the first point in time; and calculate the measurement of write memory bandwidth as being equal to a difference between the second value and the first value divided by a number of clock cycles that elapsed between the first point in time and the second point in time.

5 . The processor as recited in claim 1 , wherein the control unit is further configured to:
maintain a plurality of counters for a plurality of different thread classes, wherein each counter tracks a write memory bandwidth for a separate thread class; detect a first write to a given cache line since the given cache line has entered the cache hierarchy; and increment a counter that corresponds to a thread class to which the given cache line belongs.

6 . The processor as recited in claim 1 , wherein the control logic is further configured to add the measurement of write memory bandwidth to a given measurement of read memory bandwidth to calculate a total memory bandwidth.

7 . The processor as recited in claim 6 , wherein the control logic is further configured to compare the total memory bandwidth to one or more thresholds.

8 . A method comprising:
incrementing, by a control unit, counter when a cache line is modified for a first time since the cache line entered a cache hierarchy; generating a measurement of write memory bandwidth based on a value of the counter; and causing a number of write operations that are conveyed to a memory subsystem to be reduced responsive to the measurement of write memory bandwidth exceeding a given threshold.

9 . The method as recited in claim 8 , further comprising:
detecting a write operation targeting a first cache line; and incrementing the counter responsive to determining that the write operation to the first cache line is a first modification of the first cache line since the first cache line entered the cache hierarchy.

10 . The method as recited in claim 9 , further comprising keeping the counter unchanged responsive to determining that the write to the first cache line is not the first modification of the first cache line since the first cache line entered the cache hierarchy.

11 . The method as recited in claim 8 , further comprising:
recording a first value of the counter at a first point in time; recording a second value of the counter at a second point in time, wherein the second point in time is subsequent to the first point in time; and calculating the measurement of write memory bandwidth as being equal to a difference between the second value and the first value divided by a number of clock cycles that elapsed between the first point in time and the second point in time.

12 . The method as recited in claim 8 , further comprising:
maintaining a plurality of counters for a plurality of different thread classes, wherein each counter tracks a write memory bandwidth for a separate thread class; detecting a first write to a given cache line since the given cache line has entered the cache hierarchy; and incrementing a counter that corresponds to a thread class to which the given cache line belongs.

13 . The method as recited in claim 8 , further comprising adding the measurement of write memory bandwidth to a given measurement of read memory bandwidth to calculate a total memory bandwidth.

14 . The method as recited in claim 8 , further comprising comparing the total memory bandwidth to one or more thresholds.

15 . A system comprising:
a memory subsystem; and a processor coupled to the memory subsystem; wherein the processor is configured to:
increment a counter when a cache line is modified for a first time since the cache line entered a cache hierarchy;
generate a measurement of write memory bandwidth based on a value of the counter; and
cause a number of write operations that are conveyed to a memory subsystem to be reduced responsive to the measurement of write memory bandwidth exceeding a given threshold.

16 . The system as recited in claim 15 , wherein the processor is further configured to:
detect a write operation targeting a first cache line; and increment the counter responsive to determining that the write operation to the first cache line is a first modification of the first cache line since the first cache line entered the cache hierarchy.

17 . The system as recited in claim 16 , wherein the processor is further configured to keep the counter unchanged responsive to determining that the write to the first cache line is not the first modification of the first cache line since the first cache line entered the cache hierarchy.

18 . The system as recited in claim 15 , wherein the processor is further configured to:
record a first value of the counter at a first point in time;
record a second value of the counter at a second point in time, wherein the second point in time is subsequent to the first point in time; and
calculate the measurement of write memory bandwidth as being equal to a difference between the second value and the first value divided by a number of clock cycles that elapsed between the first point in time and the second point in time.

19 . The system as recited in claim 15 , wherein the processor is further configured to:
maintain a plurality of counters for a plurality of different thread classes, wherein each counter tracks a write memory bandwidth for a separate thread class; detect a first write to a given cache line since the given cache line has entered the cache hierarchy; and increment a counter that corresponds to a thread class to which the given cache line belongs.

20 . The system as recited in claim 15 , wherein the control logic is further configured to add the measurement of write memory bandwidth to a given measurement of read memory bandwidth to calculate a total memory bandwidth.

Assignees

• Advanced Micro Devices Inc

Inventors

• Moyer Paul James
• Hunt Douglas Benson

Classifications

• G06F12/126 Primary

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0891 Primary

  using clearing, invalidating or resetting means · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title