Method and Apparatus for Increasing Memory Level Parallelism by Reducing Miss Status Holding Register Allocation in Caches

Patent metadata

Field	Value
Publication number	US-2024202116-A1
Application number	US-202218068930-A
Country	US
Kind code	A1
Filing date	Dec 20, 2022
Priority date	Dec 20, 2022
Publication date	Jun 20, 2024
Grant date	—

Abstract

An entry of a last level cache shadow tag array to track pending last level cache misses to private data in a previous level cache (e.g., an L2 cache), that also are misses to an exclusive last level cache (e.g., an L3 cache) and to the last level cache shadow tag array. Accordingly, last level cache miss status holding registers need not be expended to track cache misses to private data that are already being tracked by a previous level cache miss status holding register. Additionally or alternatively, up to a threshold number of last level cache pending misses to the same shared data from different processor cores are tracked in the last level cache shadow tag array, and any additional last level cache pending misses are tracked in a last level cache miss status holding register.

First claim

What is claimed is:

1 . A method comprising:
receiving, at a current level cache, a physical address corresponding to a cache miss at an immediately preceding level cache; and in response to a cache miss at the current level cache and a shadow tag array miss at the current level cache:
recording the cache miss at the current level cache in the shadow tag array; and
sending, to a memory system, a request for data stored at the physical address.

2 . The method of claim 1 , the recording the cache miss at the current level cache in the shadow tag array including recording the cache miss at the current level cache in the shadow tag array without reserving a current level cache miss status holding register.

3 . The method of claim 1 , wherein recording the cache miss includes setting a current level cache pending miss indicator in an entry of the shadow tag array.

4 . The method of claim 1 , further comprising:
receiving, from the memory system, the data stored at the physical address; marking, in an entry of the shadow tag array corresponding to the cache miss at the current level cache, that the cache miss at the current level cache is no longer pending; and returning the data to a first processor core requesting the data.

5 . The method of claim 4 , further comprising:
returning the data to a second processor core indicated in the entry of the shadow tag array.

6 . The method of claim 1 , further comprising, in response to the cache miss at the current level cache and a shadow tag array hit at the current level cache:
recording the cache miss at the current level cache in an existing entry in the shadow tag array without sending the request to the memory system.

7 . The method of claim 1 , wherein the current level cache comprises a level 3 cache and the immediately preceding level cache comprises a level 2 cache.

8 . A method comprising:
receiving, at a current level cache, a physical address corresponding to a cache miss at an immediately preceding level cache for a first processor core; and in response to a cache miss at the current level cache and a shadow tag array hit at the current level cache:
recording the cache miss at the current level cache for the first processor core in an entry of the shadow tag array, the entry of the shadow tag array already recording a cache miss at the current level cache for a second processor core.

9 . The method of claim 8 , further comprising:
recording, in response to available space being present in the entry of the shadow tag array, the cache miss at the current level cache for the first processor core in the entry of the shadow tag array; and tracking, in response to available space not being present in the entry of the shadow tag array, the cache miss at the current level cache for the first processor core in a shared data miss queue miss status holding register at the current cache level.

10 . The method of claim 8 , further comprising recording the cache miss at the current level cache for the first processor core without sending a request for data stored at the physical address to a memory system.

11 . The method of claim 8 , further comprising:
receiving, from a memory system, data stored at the physical address; marking, in the entry of the shadow tag array corresponding to the cache miss at the current level cache, that the cache miss at the current level cache is no longer pending for the second processor core; and returning the data to the second processor core requesting the data.

12 . The method of claim 11 , further comprising:
marking, in the entry of the shadow tag array corresponding to the cache miss at the current level cache, that the cache miss at the current level cache is no longer pending for the first processor core; and returning the data to the first processor core requesting the data.

13 . The method of claim 8 , wherein the current level cache comprises a level 3 cache and the immediately preceding level cache comprises a level 2 cache.

14 . A device, comprising:
a current level cache to receive a physical address corresponding to a cache miss at an immediately preceding level cache and send, to a memory system, a request for data stored at the physical address; and a shadow tag array to record, in response to a cache miss at the current level cache and a shadow tag array miss at the current level cache, the cache miss at the current level cache in an entry of the shadow tag array.

15 . The device of claim 14 , wherein to record the cache miss at the current level cache in the shadow tag array includes recording the cache miss at the current level cache in the entry of the shadow tag array without reserving a current level cache miss status holding register.

16 . The device of claim 14 , wherein to record the cache miss includes setting a current level cache pending miss indicator in the entry of the shadow tag array.

17 . The device of claim 14 , wherein the current level cache is further to receive, from the memory system, the data stored at the physical address and return the data to a first processor core requesting the data, and the shadow tag array is to mark, in the entry of the shadow tag array, that the cache miss at the current level cache is no longer pending.

18 . The device of claim 17 , wherein the current level cache is further to return the data to a second processor core indicated in the entry of the shadow tag array.

19 . The device of claim 14 , wherein the shadow tag array is further to, in response to the cache miss at the current level cache and a shadow tag array hit at the current level cache, record the cache miss at the current level cache in an existing entry in the shadow tag array without sending the request to the memory system.

20 . The device of claim 14 , wherein the current level cache comprises a level 3 cache and the immediately preceding level cache comprises a level 2 cache.

Assignees

• Advanced Micro Devices Inc

Inventors

• Kotra Jagadish B
• Kalamatianos John
• Moyer Paul James
• Lance Nicholas Dean
• Srinivasan Sriram
• Shyvers Patrick James
• Walker William Louie

Classifications

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F2212/1028

  Power efficiency · CPC title