Cache Data Distribution for a Stacked Die Configuration

Patent metadata

Field	Value
Publication number	US-2025307162-A1
Application number	US-202418621610-A
Country	US
Kind code	A1
Filing date	Mar 29, 2024
Priority date	Mar 29, 2024
Publication date	Oct 2, 2025
Grant date	—

Abstract

An example system may include a first physical memory integrated within a first die, and a second physical memory integrated within a second die. The first die and second die are coupled in a stack arrangement. The system may also include a cache controller configured to implement a plurality of cache ways of a set associative cache. The plurality of cache ways include a first cache way defined within the first physical memory and a second cache way defined within the second physical memory.

First claim

What is claimed is:

1 . A system comprising:
a first physical memory integrated within a first die; a second physical memory integrated within a second die, wherein the first die and second die are coupled in a stack arrangement; and a cache controller configured to implement a plurality of cache ways of a set associative cache, the plurality of cache ways including a first cache way defined within the first physical memory and a second cache way defined within the second physical memory.

2 . The system of claim 1 , wherein the cache controller is further configured to select one of the plurality of cache ways to cache data in the set associative cache or to evict the cached data from the set associative cache.

3 . The system of claim 2 , wherein the cache controller is configured to select the one of the plurality of cache ways based at least in part on die characteristics of the first die and the second die.

4 . The system of claim 3 , wherein the die characteristics include at least one of latency, data communication bandwidth, or memory space availability.

5 . The system of claim 2 , wherein the cache controller is configured to select the one of the plurality of cache ways based at least in part on data characteristics of the cached data.

6 . The system of claim 5 , wherein the data characteristics include at least one of data access frequency or quality of service metrics associated with the cached data.

7 . The system of claim 2 , wherein the cache controller is configured to select the one of the plurality of cache ways based at least in part on a state of a system component associated with the data.

8 . The system of claim 7 , wherein the state of the system component includes at least one of the system component requesting the data as part of a pre-fetch command, or the system component requesting the data for execution.

9 . The system of claim 2 , wherein the cache controller is further configured to select the one of the plurality of cache ways based at least in part on a power consumption of the system or a system component.

10 . The system of claim 9 , wherein the cache controller is further configured to, in response to the power consumption exceeding a threshold level:
transfer cached data out of the second physical memory; update the set associative cache to remove the second cache way from the plurality of cache ways; and reduce an amount of power provided to the second die.

11 . A device comprising:
a first physical memory integrated within a first die; and a cache controller, the cache controller configured to:
map a plurality of cache ways of a set associative cache, the plurality of cache ways including a first cache way defined within the first physical memory;
detect that a second die is coupled to the first die in a stack arrangement, the second die including a second physical memory integrated within the second die; and
update the plurality of cache ways to include a second cache way defined within the second physical memory.

12 . The device of claim 11 , wherein the cache controller is configured to update the plurality of cache ways in response to the detection of the second die.

13 . The device of claim 11 , wherein the cache controller is further configured to select one of the plurality of cache ways to cache data in the set associative cache or to evict the data from the set associative cache.

14 . The device of claim 13 , wherein the cache controller is configured to select the one of the plurality of cache ways based at least in part on die characteristics of the first die and the second die.

15 . The device of claim 13 , wherein the cache controller is configured to select the one of the plurality of cache ways based at least in part on data characteristics of the data.

16 . The device of claim 13 , wherein the cache controller is configured to select the one of the plurality of cache ways based at least in part on a state of a system component associated with the data.

17 . A method comprising:
mapping a plurality of cache ways of a set associative cache, the plurality of cache ways including a first cache way defined to be within a first physical memory, the first physical memory being integrated within a first die; detecting that a second die is coupled to the first die in a stack arrangement and that a second physical memory is integrated within the second die; and updating the plurality of cache ways to include a second cache way defined to be within the second physical memory.

18 . The method of claim 17 , wherein updating the plurality of cache ways is in response to the detection of the second die.

19 . The method of claim 17 , further comprising selecting one of the plurality of cache ways to cache data in the set associative cache or to evict the cached data from the set associative cache.

20 . The method of claim 19 , wherein selecting the one of the plurality of cache ways is based at least in part on die characteristics of the first die and the second die.

Assignees

• Advanced Micro Devices Inc

Inventors

• Schoenwald Matthew Donald
• Moyer Paul James
• Walker William Louie

Classifications

• G06F2212/6032

  Way prediction in set-associative cache · CPC title

• G06F12/0864 Primary

  using pseudo-associative means, e.g. set-associative or hashing · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title