Oldest operation wait time indication input into set-dueling

Patent metadata

Field	Value
Publication number	US-2021073126-A1
Application number	US-201916562101-A
Country	US
Kind code	A1
Filing date	Sep 5, 2019
Priority date	Sep 5, 2019
Publication date	Mar 11, 2021
Grant date	—

Abstract

Systems, apparatuses, and methods for dynamically adjusting cache policies to reduce execution core wait time are disclosed. A processor includes a cache subsystem. The cache subsystem includes one or more cache levels and one or more cache controllers. A cache controller partitions a cache level into two test portions and a remainder portion. The cache controller applies a first policy to the first test portion and applies a second policy to the second test portion. The cache controller determines the amount of time the execution core spends waiting on accesses to the first and second test portions. If the measured wait time is less for the first test portion than for the second test portion, then the cache controller applies the first policy to the remainder portion. Otherwise, the cache controller applies the second policy to the remainder portion.

First claim

What is claimed is:

1 . A cache subsystem comprising:
a cache; and a cache controller coupled to the cache, wherein the cache controller is configured to:
apply a first policy to a first cache portion and apply a second policy to a second cache portion;
determine an amount of time that an execution core spends waiting on instructions to access each of the first cache portion and the second cache portion;
apply the first policy to a third cache portion, responsive to a first wait time for the first cache portion being less than a second wait time for the second cache portion; and
apply the second policy to the third cache portion, responsive to the second wait time being less than the first wait time.

2 . The processor as recited in claim 1 , wherein the first policy specifies one or more of a cache line replacement policy, cache line insertion policy, request priority, speculation hint generation, or pre-emptive response generation for the first cache portion.

3 . The processor as recited in claim 1 , wherein the control unit is configured to receive an identifier of a pending cache access generated by the execution core.

4 . The processor as recited in claim 3 , wherein control unit is configured to receive a valid bit with an identifier to indicate that an instruction corresponding to the pending cache access is on a performance-critical path.

5 . The processor as recited in claim 1 , wherein responsive to the first wait time for the first cache portion being less than the second wait time for the second cache portion, the control unit is configured to:
create a third policy; apply the third policy to the second cache portion while applying the first policy to the first cache portion; and apply the third policy to the third cache portion responsive to a third wait time for the second cache portion being less than a fourth wait time for the first cache portion.

6 . The processor as recited in claim 5 , wherein one or more attributes of the third policy are randomly generated.

7 . The processor as recited in claim 1 , wherein the first wait time is equal to an average number of clock cycles that the execution core spends waiting for an access to the first cache portion.

8 . A method comprising:
applying, by a control unit, a first policy to a first cache portion and a second policy to a second cache portion; determining a first wait time that an execution core spends waiting on instructions to access the first cache portion; determining a second wait time that the execution core spends waiting on instructions to access the second cache portion; applying the first policy to a third portion of the cache responsive to the first wait time for the first cache portion being less than the second wait time for the second cache portion; and applying the second policy to the third portion of the cache responsive to the second wait time being less than the first wait time.

9 . The method as recited in claim 8 , wherein the first policy specifies one or more of cache line replacement policy, cache line insertion policy, request priority, speculation hint generation, and pre-emptive response generation for the first cache portion.

10 . The method as recited in claim 8 , further comprising receiving an identifier of a pending cache access generated by the execution core.

11 . The method as recited in claim 10 , further comprising receiving a valid bit with an identifier to indicate that an instruction corresponding to the pending cache access is on a performance-critical path.

12 . The method as recited in claim 8 , wherein responsive to the first wait time for the first cache portion being less than the second wait time for the second cache portion, the method further comprising:
creating a third policy; applying the third policy to the second cache portion while applying the first policy to the first cache portion; and applying the third policy to the third cache portion responsive to a third wait time for the second cache portion being less than a fourth wait time for the first cache portion.

13 . The method as recited in claim 12 , wherein one or more attributes of the third policy are randomly generated.

14 . The method as recited in claim 8 , wherein the first wait time is equal to an average number of clock cycles that the execution core spends waiting for an access to the first cache portion.

15 . A system comprising:
a memory; and
a processor coupled to the memory;
wherein the processor is configured to:
apply a first policy to a first cache portion and apply a second policy to a second cache portion;
determine a first wait time that an execution core spends waiting on instructions to access the first cache portion;
determine a second wait time that the execution core spends waiting on instructions to access the second cache portion;
apply the first policy to a third cache portion responsive to the first wait time for the first cache portion being less than the second wait time for the second cache portion; and
apply the second policy to the third cache portion responsive to the second wait time for the second cache portion being less than the first wait time for the first cache portion.

16 . The system as recited in claim 15 , wherein the first policy specifies one or more of cache line replacement policy, cache line insertion policy, request priority, speculation hint generation, and pre-emptive response generation for the first cache portion.

17 . The system as recited in claim 15 , wherein the execution core is configured to send, to a control unit, identifiers (IDs) of instructions of oldest pending cache accesses.

18 . The system as recited in claim 15 , wherein the execution core is configured to send, to the control unit, a valid bit with an ID to indicate if a corresponding instruction is on a performance-critical path.

19 . The system as recited in claim 15 , wherein responsive to the first wait time for the first cache portion being less than the second wait time for the second cache portion, the processor is further configured to:
create a third policy; apply the third policy to the second cache portion while applying the first policy to the first cache portion; and apply the third policy to the third cache portion responsive to a third wait time for the second cache portion being less than a fourth wait time for the first cache portion.

20 . The system as recited in claim 19 , wherein one or more attributes of the third policy are randomly generated.

Assignees

• Advanced Micro Devices Inc

Inventors

• Moyer Paul James

Classifications

• G06F2212/6046

  Using a specific cache allocation policy other than replacement policy · CPC title

• G06F12/0893 Primary

  Caches characterised by their organisation or structure · CPC title

• G06F12/0877 Primary

  Cache access modes · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title