Intelligent management of forward error correction
US-2025337523-A1 · Oct 30, 2025 · US
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Kumar Shishir patents
Kumar Shishir is listed as an inventor on 59 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kumar Shishir |
| Total patents | 59 |
| First publication | Jan 29, 2015 |
| Latest publication | Oct 30, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Intelligent management of forward error correction
US-12457056-B1 · Oct 28, 2025 · US
Voltage calibration for write operation
US-2025322863-A1 · Oct 16, 2025 · US
Localized and relocatable software placement and noc-based access to memory controllers
US-2025321675-A1 · Oct 16, 2025 · US
Localized and relocatable software placement and NoC-based access to memory controllers
US-12353717-B2 · Jul 8, 2025 · US
Reducing memory device bitline leakage
US-12354656-B2 · Jul 8, 2025 · US
Interface level-shifter dual-rail memory architecture
US-12340864-B2 · Jun 24, 2025 · US
Delay circuit
US-12316326-B1 · May 27, 2025 · US
Reducing spurious write operations in a memory device
US-12272424-B2 · Apr 8, 2025 · US
Scan chain compression for testing memory of a system on a chip
US-12112818-B2 · Oct 8, 2024 · US
Recent patents
Latest publications not already listed above.
Power supply tracking circuitry for embedded memories
US-12094513-B2 · Sep 17, 2024 · US
Localized and relocatable software placement and noc-based access to memory controllers
US-2024211138-A1 · Jun 27, 2024 · US
Dynamically allocated buffer pooling
US-12019908-B2 · Jun 25, 2024 · US
Reducing Memory Device Bitline Leakage
US-2024038300-A1 · Feb 1, 2024 · US
Dual port memory cell with improved access resistance
US-11889675-B2 · Jan 30, 2024 · US
Reducing spurious write operations in a memory device
US-2023307019-A1 · Sep 28, 2023 · US
Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory
US-11742045-B2 · Aug 29, 2023 · US
Interface level-shifter dual-rail memory architecture
US-2023260555-A1 · Aug 17, 2023 · US
Power supply tracking circuitry for embedded memories
US-2023125268-A1 · Apr 27, 2023 · US
Dual port memory cell with improved access resistance
US-2023091970-A1 · Mar 23, 2023 · US
Dynamically allocated buffer pooling
US-2023036531-A1 · Feb 2, 2023 · US
Scan chain compression for testing memory of a system on a chip
US-2023005562-A1 · Jan 5, 2023 · US
Dual port memory cell with improved access resistance
US-11532633-B2 · Dec 20, 2022 · US
Circuit and method for at speed detection of a word line fault condition in a memory circuit
US-11521697-B2 · Dec 6, 2022 · US
Circuit and method for at speed detection of a word line fault condition in a memory circuit
US-11393532-B2 · Jul 19, 2022 · US
Dual port memory cell with improved access resistance
US-2022020754-A1 · Jan 20, 2022 · US
Robust adaptive method and circuit for controlling a timing window for enabling operation of sense amplifier
US-11195576-B2 · Dec 7, 2021 · US
Dual port memory cell with improved access resistance
US-11152376-B2 · Oct 19, 2021 · US
Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory
US-2021225453-A1 · Jul 22, 2021 · US
Circuit for detection of single bit upsets in generation of internal clock for memory
US-11025252-B2 · Jun 1, 2021 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| St Microelectronics Int Nv | 26 |
| Synopsys Inc | 12 |
| Wipro Ltd | 8 |
| St Microelectronics Int Nv | 6 |
| Xilinx Inc | 5 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/417 | 13 |
| G11C11/419 | 13 |
| G11C11/412 | 10 |
| G11C29/44 | 8 |
| G11C7/222 | 8 |