Circuit for detection of single bit upsets in generation of internal clock for memory

Patent metadata

Field	Value
Publication number	US-11025252-B2
Application number	US-201916578487-A
Country	US
Kind code	B2
Filing date	Sep 23, 2019
Priority date	Sep 24, 2018
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A failure determination circuit includes a latch circuit that receives an internal clock from a clock latch that rises in response to an external clock rising. In response to a rising edge of the external clock, the circuit generates a rising edge of a fault flag. In response to a rising edge of the internal clock if it occurs, the fault flag falls. The fault flag is then latched. The latched fault flag indicates a single bit upset in the clock latch if the falling edge of the fault flag was not generated prior to latching, if the clock latch is in an active mode, and indicates a single bit upset in the clock latch if the falling edge of the fault flag was generated prior to latching, if the clock latch is in an inactive mode.

First claim

The invention claimed is:

1. A failure determination circuit, comprising:
a master and save latch arrangement configured, in an active mode, to:
directly electrically receive an internal clock signal from a clock latch that is intended to rise in response to an external clock signal rising, wherein the internal clock signal is generated from the external clock signal;
generate a rising edge of a fault flag signal in response to a rising edge of the external clock signal;
generate a falling edge of the fault flag signal in response to a rising edge of the internal clock signal if the rising edge of the internal clock signal occurs;
latch the fault flag signal in response to a falling edge of the internal clock signal; and
wherein the latched fault flag signal indicates a single bit upset in the clock latch if the falling edge of the fault flag signal was not generated prior to latching.

2. The failure determination circuit of claim 1 , wherein the master and slave latch arrangement is configured, in an inactive mode, to:
generate a rising edge of a fault flag signal in response to a rising edge of the external clock signal;
generate a falling edge of the fault flag signal in response to a rising edge of the internal clock signal if the rising edge of the internal clock signal occurs; and
latch the fault flag signal in response to a falling edge of the internal clock signal if the rising edge of the internal clock signal occurred;
wherein the latched fault flag signal indicates a single bit upset in the clock latch if the falling edge of the fault flag signal was generated prior to latching.

3. A failure determination circuit, comprising:
a master and save latch arrangement configured, in an active mode, to:
receive an internal clock signal from a clock latch that is intended to rise in response to an external clock signal rising, wherein the internal clock signal is generated from the external clock signal;
generate a rising edge of a fault flag signal in response to a rising edge of the external clock signal;
generate a falling edge of the fault flag signal in response to a rising edge of the internal clock signal if the rising edge of the internal clock signal occurs;
latch the fault flag signal in response to a falling edge of the internal clock signal; and
wherein the latched fault flag signal indicates a single bit upset in the clock latch if the falling edge of the fault flag signal was not generated prior to latching;

wherein the master and slave latch arrangement comprises:
a first latch having a first input receiving an inverse of the external clock signal, a second input receiving the internal clock signal, and an output;
an inverter coupled to the output of the first latch; and
a second latch having a non-inverting enable terminal receiving a signal based upon the inverse of the external clock signal and an inverse of the output of the first latch, an inverting enable terminal receiving a signal based upon the internal clock signal, an input coupled to receive output from the inverter, and an output.

4. The failure determination circuit of claim 3 , wherein the first latch comprises a NOR logic circuit; and wherein the second latch comprises a NOT logic circuit.

5. The failure determination circuit of claim 3 , wherein the second latch comprises:
a first tri-state inverter having an inverting enable terminal receiving the inverse of the external clock signal, a non-inverting enable terminal receiving the internal clock signal, and an input coupled to receive output from the inverter;
a first inverter having an input coupled to an output of the first tri-state inverter; and
a second tri-state inverter having an inverting enable terminal, a non-inverting enable terminal, an input coupled to an output of the first inverter, and an output coupled to the input of the first inverter.

6. The failure determination circuit of claim 5 , wherein the second latch further comprises:
a PMOS transistor having a source coupled to a supply node, a drain coupled to the inverting enable terminal of the second tri-state inverter, and a gate coupled to the internal clock signal;
a first NMOS transistor having a drain coupled to the non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to receive output from the inverter that receives output of the first latch;
a second NMOS transistor having a drain coupled to the non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to the inverse of the external clock signal; and
an inverter receiving input from the first inverter and producing the fault flag signal at its output.

7. A failure determination circuit that detects a single bit upset in a clock latch, the clock latch receiving an external clock signal and generating an internal clock signal therefrom, the failure determination circuit comprising:
a first latch configured to generate a first signal at logic high when the internal clock signal is at logic low and the external clock signal is at logic high, and generate the first signal at logic low when the internal clock signal is at logic high; and
a second latch configured to generate a fault flag signal at logic high when the first signal is at logic high, generate the fault flag signal at logic low when the first signal is at logic low, and latch when the internal clock signal is at logic low;
wherein presence of a single bit upset in the clock latch is indicated by the fault flag signal being at logic high upon latching of the second latch and the clock latch being in an active mode; and
wherein presence of a single bit upset in the clock latch is indicated by the fault flag signal being at logic low upon latching of the second latch and the clock latch being in an inactive mode.

8. The failure determination circuit of claim 7 , wherein the second latch comprises:
a first tri-state inverter having an inverting enable terminal receiving the inverse of the external clock signal, a non-inverting enable terminal receiving the internal clock signal, and an input coupled to receive an inverted version of the first signal;
a first inverter having an input coupled to an output of the first tri-state inverter;
a second tri-state inverter having an inverting enable terminal, a non-inverting enable terminal, an input coupled to an output of the first inverter, and an output coupled to the input of the first inverter;
a PMOS transistor having a source coupled to a supply node, a drain coupled to the inverting enable terminal of the second tri-state inverter, and a gate coupled to the internal clock signal;
a first NMOS transistor having a drain coupled to the non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to receive output from the inverter that receives output of the first latch;
a second NMOS transistor having a drain coupled to the non-inverting enable terminal of the second tri-state inverter, a source coupled to ground, and a gate coupled to the inverse of the external clock signal; and
an inverter receiving input from the first inverter and producing the fault flag signal at its output.

9. The failure determination circuit of claim 8 , wherein the first latch comprises:
first and second NOR gates;
wherein the first NOR gate has inputs coupled to the inverse of the external clock signal and to the output of the second NOR gate, and an output;
wherein the second NOR gate has inputs coupled to the internal clock signal and to the output of the first NOR gate, and an output; and
a third inverter coupled to receive input from the output of the second NOR gate and providing ou

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Shishir
• Kumar Tanuj
• Bihani Deepak Kumar

Classifications

• H03K17/223 Primary

  in field-effect transistor switches · CPC title

• G01R31/2843

  In-circuit-testing · CPC title

• H03K19/00315 Primary

  in field-effect transistor circuits · CPC title