Circuit and method for at speed detection of a word line fault condition in a memory circuit

Patent metadata

Field	Value
Publication number	US-11521697-B2
Application number	US-202016742292-A
Country	US
Kind code	B2
Filing date	Jan 14, 2020
Priority date	Jan 30, 2019
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.

First claim

What is claimed is:

1. A circuit, comprising:
a first memory array including a plurality of word lines;
a row decoder located on one side of the first memory array and configured to selectively drive the plurality of word lines in response to a row address; and
a first word line fault detection circuit located on an opposite side of the first memory array, the first word line fault detection circuit comprising:
a first clamp circuit configured to clamp the plurality of word lines at the opposite side of the first memory array to ground in response to a change in logic state of a clamp control signal;
a first encoder circuit configured to encode signals on the plurality of word lines at the opposite side of the first memory array to generate a first encoded address; and
a first comparator circuit configured to receive the clamp control signal and in response to said change in logic state compare the first encoded address to the row address and set a first error flag indicating presence of an open word line fault between said one side and said opposite side of the first memory array if the first encoded address does not match the row address;

wherein the clamp control signal propagates on a signal line from an output of a control circuit to the first clamp circuit and further propagates from the first clamp circuit to an input of the first comparator circuit, and
wherein a propagation time for the clamp control signal on the signal line from the output of the control circuit to the input of the first comparator circuit is sufficient for the first encoder circuit to complete encoding of the signals on the plurality of word lines to generate the first encoded address for comparison by the first comparator circuit.

2. The circuit of claim 1 , further comprising a control circuit configured to actuate the first clamp circuit through the change in logic state of the clamp control signal and apply the row address to the row decoder and then deactuate the first clamp circuit prior to the first encoder circuit operation to encode the signals on the plurality of word lines and generate the first encoded address.

3. The circuit of claim 2 , wherein the first clamp circuit comprises a plurality of transistors connected to the plurality of word lines at the opposite side of the first memory array, the plurality of transistors having gate terminals coupled to receive the clamp control signal output from the control circuit and the plurality of transistors being configured to electrically connect the plurality of word lines to ground.

4. The circuit of claim 1 , wherein the first encoder circuit is an M×N encoder, wherein M is equal to the number of word lines and N is equal to the number of bits in the row address.

5. The circuit of claim 1 , wherein the first encoder circuit is further configured to encode signals on the plurality of word lines to generate a complement first encoded address and wherein the comparator circuit is further configured to compare the complement first encoded address to a complement of the row address and set the first error flag if the complement first encoded address does not match the complement row address.

6. The circuit of claim 1 , wherein the clamp of the plurality of word lines to ground discharges accumulated charge on a portion of a word line which is floating due to the presence of the open word line fault between said one side and said opposite side of the first memory array.

7. The circuit of claim 1 , further comprising:
a second memory array including said plurality of word lines;
wherein said row decoder is located on one side of the second memory array; and
a second word line fault detection circuit located on an opposite side of the second memory array, the second word line fault detection circuit comprising:
a second clamp circuit configured to clamp the plurality of word lines at the opposite side of the second memory array to ground;
a second encoder circuit configured to encode signals on the plurality of word lines at the opposite side of the second memory array to generate a second encoded address; and
a second comparator circuit configured to compare the second encoded address to the row address and set a second error flag indicating presence of the open word line fault if the second encoded address does not match the row address.

8. The circuit of claim 7 , further comprising a control circuit configured to actuate the first and second clamp circuits through the change in logic state of the clamp control signal and apply the row address to the row decoder and then deactuate the first and second clamp circuits prior to the first and second encoder circuits operating to encode the signals on the plurality of word lines and generate the first and second encoded address.

9. The circuit of claim 8 , wherein each of the first and second clamp circuits comprises a plurality of transistors connected to the plurality of word lines at the opposite side of the first memory array, the plurality of transistors having gate terminals coupled to receive the clamp control signal output from the control circuit and the plurality of transistors being configured to electrically connect the plurality of word lines to ground.

10. The circuit of claim 7 , wherein each of the first and second first encoder circuits is an M×N encoder, wherein M is equal to the number of word lines and N is equal to the number of bits in the row address.

11. The circuit of claim 7 , wherein each of the first and second first encoder circuits is an M×N encoder, wherein M is equal to the number of word lines and N is equal to a fraction of the number of bits in the row address.

12. The circuit of claim 11 , wherein the fraction is one divided by the number of memory arrays.

13. The circuit of claim 7 , wherein the first and second encoder circuits are further configured to encode signals on the plurality of word lines to generate a complement first encoded address and complement second encoded address, respectively, and wherein the first and second comparator circuits are further configured to compare the complement first and second encoded addresses to a complement of the row address, respectively, and set the first and second error flags if the addresses do not match.

14. A method, comprising:
decoding a row address to selectively drive a plurality of word lines of a first memory array at one side of the first memory array;
clamping the plurality of word lines to ground at an opposite side of the first memory array in response to a change in logic state of a clamp control signal;
encoding signals on the plurality of word lines at the opposite side of the first memory array to generate a first encoded address;
in response to said change in logic state of the clamp control signal, comparing the first encoded address to the row address;
setting a first error flag indicating presence of an open word line fault between said one side and said opposite side of the first memory array if the first encoded address does not match the row address; and
propagating said clamp control signal over a signal line to a clamp circuit performing said clamping and further to a comparison circuit performing said comparing;
wherein a propagation time for the clamp control signal along the signal line to the comparison circuit is sufficient for completing said encoding signals on the plurality of word lines to generate the first encoded address for comparison to the row address.

15. The method of claim 14 , further comprising releasing the clamping of the plurality of word lines prior to encoding the signals on the plurality of

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Shishir
• Pathak Abhishek

Classifications

• G11C29/38 Primary

  Response verification devices · CPC title

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• G11C2029/1202

  Word line control · CPC title

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/12

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title