Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory

Patent metadata

Field	Value
Publication number	US-11742045-B2
Application number	US-202117222119-A
Country	US
Kind code	B2
Filing date	Apr 5, 2021
Priority date	Jan 8, 2019
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

First claim

What is claimed is:

1. An apparatus, comprising:
comparison circuitry including a plurality of comparator circuits and a logic circuit for logically combining outputs of the comparator circuits to generate an output signal;
wherein each comparator circuit is configured to compare a bit of a first bus to a bit of a second bus; and
a testing circuit configured to test the comparator circuits of the comparison circuitry for a stuck-at-1 fault by:
applying a force signal to the first bus, wherein all bits of the force signal have a same logic state;
applying a testing signal to the second bus, wherein one bit of the testing signal has a first logic state and all other bits of the testing signal have a second logic state; and
monitoring for a logic state of the output signal indicative that the comparator circuit which received said one bit of the testing signal having the first logic state is in a stuck-at-1 fault condition.

2. The apparatus of claim 1 , further comprising:
an encoder circuit configured to encode a plurality of select signals to generate an encoded address signal;
a blocking circuit configured to selectively pass the encoded address signal to the first bus; and
wherein said testing circuit is configured to actuate the blocking circuit to block passage of the encoded address signal to the first bus during a time period where testing of the comparator circuits of the comparison circuitry is being performed.

3. The apparatus of claim 1 , wherein the testing circuit is selectively enabled to perform the test of each comparator circuit of the comparison circuitry in response to a subset of the memory built-in self-test (MBIST) scan routine.

4. The apparatus of claim 3 , wherein the logic state of the output signal is monitored by the MBIST.

5. The apparatus of claim 3 , wherein the second bus is an address bus, and wherein the plurality of select signals are generated by decoding bits on said address bus.

6. The apparatus of claim 1 , wherein the logic circuit operates to logically AND outputs of the comparator circuits.

7. The apparatus of claim 1 , wherein the first bus comprises a true bus portion and a complement bus portion, and wherein all bits of the force signal on the true bus portion have one logic state and wherein all bits of the force signal on the complement bus portion have another logic state.

8. The apparatus of claim 7 , wherein each comparator circuit comprises:
a first logical NAND gate configured to logically combine a bit of the true bus portion, a complementary bit of the complement bus portion and a bit of the second bus;
a logical NOR gate configured to logically combine said bit of the true bus portion, said complementary bit of the complement bus portion and said bit of the second bus;
an inverter configured to logically invert an output of the logical NOR gate; and
a second logical NAND gate configured to logically combine an output of the first logical NAND gate and an output of the inverter.

9. The apparatus of claim 1 , wherein the logic circuit for logically combining outputs of the comparator circuits comprises a logical NAND gate.

10. The apparatus of claim 9 , wherein the logic circuit further comprises a logical XNOR gate configured to logically combine an output of the logical NAND gate and a test control signal.

11. An apparatus, comprising:
a comparison circuit coupled to a first bus and a second bus and configured to compare a first address on the first bus to a second address on the second bus and generate a test result signal in response to the comparison;
a testing circuit configured to test the comparison circuit for a stuck-at-1 fault, said testing circuit comprising:
a blocking circuit configured to block the first address from application to the first bus; and
a test control circuit configured to apply a force signal to the first bus, with said second bus configured to receive a built-in self-test (BIST) signal, the force signal and the BIST signal being configured to the test the comparison circuit so that the test result signal generated by the comparison circuit in response to the comparison is indicative of whether the comparison circuit suffers from said stuck-at-1 fault.

12. The apparatus of claim 11 , wherein the comparison circuit comprises a plurality of bit comparator circuits configured to compare bits of the first bus to corresponding bits of the second bus, and wherein the BIST signal selectively picks one bit comparator circuit of the plurality of bit comparator circuits to be tested for said stuck-at-1 fault.

13. The apparatus of claim 11 , wherein the comparison circuit comprises a plurality of bit comparator circuits configured to compare bits of the first bus to corresponding bits of the second bus, and wherein the BIST signal comprises a sequence of test signals, each test signal in the sequence configured to pick a different bit comparator circuit of the plurality of bit comparator circuits to be tested for said stuck-at-1 fault.

14. The apparatus of claim 11 , wherein a logic state of the test result signal generated by the comparison circuit indicating a matching of the first address and second address and a logic state of the test result signal generated by the comparison circuit indicating no stuck-at-1 fault are different logic states.

15. The apparatus of claim 11 , wherein a logic state of the test result signal generated by the comparison circuit indicating a matching of the first address and second address and a logic state of the test result signal generated by the comparison circuit indicating no stuck-at-1 fault are same logic states.

16. The apparatus of claim 11 , wherein the force signal forces all bits of the first bus to a same logic state.

Assignees

• St Microelectronics Int Nv

Inventors

• Bhasin Rohit
• Kumar Shishir
• Roy Tanmoy
• Bihani Deepak Kumar

Classifications

• G11C29/38 Primary

  Response verification devices · CPC title

• G11C29/14

  Implementation of control logic, e.g. test mode decoders · CPC title

• G11C29/18 Primary

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C2029/1802

  Address decoder · CPC title