Reducing memory device bitline leakage

Patent metadata

Field	Value
Publication number	US-12354656-B2
Application number	US-202217955790-A
Country	US
Kind code	B2
Filing date	Sep 29, 2022
Priority date	Aug 1, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A memory device includes a plurality of select lines, a plurality of word lines, an array of memory cells, a bitline, and a resistance device. The array of memory cells includes multiple rows and multiple columns. The bitline is structured to receive a current in a read operation, causing a value stored in a selected memory cell to be readable when a select line and a word line that interest the selected memory cell are selected. The resistance device has a first terminal and a second terminal. The first terminal is coupled to the select lines, and the second terminal is coupled to ground. The resistance device is structured to bias, in the read operation, word lines of unselected memory cells in a column of a selected memory cell to a determined negative voltage.

First claim

What is claimed is:

1. A memory device comprising:
a plurality of select lines;
a plurality of word lines;
a plurality of memory cells, having a plurality of rows and a plurality of columns;
a bitline structured to receive a current in a read operation, causing a value stored in a selected memory cell of the plurality of memory cells to be readable when a select line of the plurality of select lines and a word line of the plurality of word line that intersect the selected memory cell are both selected; and
a resistance device having a first terminal and a second terminal, wherein:
the first terminal of the resistance device is coupled to each of the plurality of select lines,
the second terminal of the resistance device is coupled to ground, and
the resistance device is to bias, in read operations, word lines of unselected memory cells to a determined negative voltage,
wherein during a first read option, a first memory cell at an intersection of a first word line and a first select line is selected, the resistance device is configured to bias word lines of unselected memory cells along the first select line, and
wherein during a second read option, a second memory cell at an intersection of a second word line and a second select line, different from the first word line and the first select line respectively, is selected, the resistance device is configured to bias word lines of unselected memory cells along the second select line,
wherein a resistance of the resistance device is computed based on one or more of: (1) a ratio of leakage reduction and required bias voltage, or (2) read current of the memory device.

2. The memory device of claim 1 , wherein the memory device is a resistance based memory device that depends upon changes of resistance to store values in memory cells.

3. The memory device of claim 1 , wherein the memory device is one of (i) a phase change memory (PCM), (ii) a magnetoresistive random access memory (MRAM), or (iii) a resistive random access memory (RRAM).

4. The memory device of claim 1 , wherein each memory cell comprises:
a MOS transistor having a gate terminal, a source terminal, and a drain terminal;
a variable resistor having a first terminal and a second terminal, wherein:
the gate terminal of the MOS transistor is connected to a corresponding word line,
the drain terminal of the MOS transistor is connected to the first terminal of the variable resistor,
the source terminal of the MOS transistor is connected to the select line,
the second terminal of the variable resistor is connected to the bitline, and
the resistance device causes a voltage of the select line to be raised to a determined voltage (+V), which in turn causes a voltage between the gate terminal and the source terminal of the MOS transistor to be the determined negative voltage (−V).

5. The memory device of claim 1 , wherein the determined negative voltage (−V) is about negative 100 mV to 200 mV.

6. The memory device of claim 1 , wherein the memory device includes at least one of a resistor, a metal-insulator-semiconductor (MOS) transistor, a polycrystalline silicon (Poly) transistor, an oxide diffusion (OD) area, a nanowire (NW) transistor, or a combination thereof.

7. The memory device of claim 1 , wherein a resistance of the resistance device is computed based on a ratio of leakage reduction and required bias voltage.

8. The memory device of claim 1 , wherein a resistance of the resistance device is computed based on read current of the memory device.

9. The memory device of claim 8 , wherein when a number of memory cells in the column is 1024, a resistance of the resistance device is about 4000 ohm.

10. The memory device of claim 1 , wherein a resistance of the resistance device is adjustable.

11. The memory device of claim 10 , wherein the memory device further comprises a resistance adjustment module configured to adjust the resistance of the resistance device based on a temperature of the memory device.

12. The memory device of claim 11 , wherein the memory device further comprises a temperature detection module configured to detect the temperature of the memory device, and responsive to detecting that the temperature of the memory device is greater than a threshold, the resistance adjustment module increases the resistance of the resistance device.

13. A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to instantiate a digital representation of a memory device, the digital representation of the memory device comprising:
a plurality of select lines;
a plurality of word lines;
a plurality of memory cells, having a plurality of rows and a plurality of columns;
a bitline structured to receive a current in a read operation, causing a value stored in a selected memory cell of the plurality of memory cells to be readable when a select line of the plurality of select lines and a word line of the plurality of word lines that intersect the selected memory cell are both selected; and
a resistance device having a first terminal and a second terminal; and
a resistance device having a first terminal and a second terminal, wherein:
the first terminal of the resistance device is coupled to each of the plurality of select lines,
the second terminal of the resistance device is coupled to ground, and
the resistance device is to bias, in read operations, word lines of unselected memory cells to a determined negative voltage,
wherein during a first read option, a first memory cell at an intersection of a first word line and a first select line is selected, the resistance device is configured to bias word lines of unselected memory cells along the first select line, and
wherein during a second read option, a second memory cell at an intersection of a second word line and a second select line, different from the first word line and the first select line respectively, is selected, the resistance device is configured to bias word lines of unselected memory cells along the second select line,
wherein a resistance of the resistance device is computed based on one or more of: (1) a ratio of leakage reduction and required bias voltage, or (2) read current of the memory device.

14. The non-transitory computer readable medium of claim 13 , wherein the memory device is a resistance based memory device that depends upon changes of resistance to store values in memory cells.

15. The non-transitory computer readable medium of claim 13 , wherein the memory device is one of (i) a phase change memory (PCM), (ii) a magnetoresistive random access memory (MRAM), or (iii) a resistive random access memory (RRAM).

16. The non-transitory computer readable medium of claim 13 , wherein each memory cell comprises:
a MOS transistor having a gate terminal, a source terminal, and a drain terminal;
a variable resistor having a first terminal and a second terminal, wherein:
the gate terminal of the MOS transistor is connected to a corresponding word line,
the drain terminal of the MOS transistor is connected to the first terminal of the variable resistor,
the source terminal of the MOS transistor is connected to the select line,
the second terminal of the variable resistor is connected to the bitline, and
the resistance device causes a voltage of the select line to be raised to a determined voltage (+V), which in turn causes a voltage between the gate terminal and the source terminal of the MOS transistor to be the determined negative voltage (−V).

17. The non-transitory computer readable me

Assignees

• Synopsys Inc

Inventors

• Kumar Shishir
• Kumar Vinay

Classifications

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C29/50008

  of impedance · CPC title

• G11C2029/5002

  Characteristic · CPC title