Dynamically allocated buffer pooling

Patent metadata

Field	Value
Publication number	US-12019908-B2
Application number	US-202117389272-A
Country	US
Kind code	B2
Filing date	Jul 29, 2021
Priority date	Jul 29, 2021
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

First claim

What is claimed is:

1. A buffer memory pool circuitry, comprising:
a plurality of buffer memory circuits forming a buffer pool circuitry, each buffer memory circuit configured to store an entry identifier, a payload portion, and a next-entry pointer; and
a processor circuitry configured to:
identify an allocation request for a first virtual channel circuit of a plurality of virtual channel circuits associated with the plurality of buffer memory circuits, each of the plurality of virtual channel circuits associated with a corresponding sequence of buffer memory circuits and comprising a start pointer identifying the entry identifier for an initial buffer memory circuit of the corresponding sequence of buffer memory circuits,
program the first virtual channel circuit to be associated with the corresponding sequence of buffer memory circuits based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit of the corresponding sequence of buffer memory circuits, and
update the next-entry pointer of a buffer memory circuit of the corresponding sequence of buffer memory circuits for the first virtual channel circuit, to reprogram the first virtual channel circuit, based on determining a fault within the corresponding sequence of buffer memory circuits for the first virtual channel circuit,

wherein a length of the corresponding sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit of the plurality of virtual channel circuits subsequent to the first virtual channel circuit.

2. The buffer memory pool circuitry of claim 1 , wherein the processor circuitry is further configured to:
identify a reprogram request to change an aspect of the first virtual channel circuit and the corresponding sequence of buffer memory circuits,
determine an update pointer value to the start pointer for the second virtual channel circuit and an update ID value to the next-entry pointer for a terminal buffer memory circuit of the corresponding sequence of buffer memory circuits based on the identified reprogram request;
update the start pointer for the second virtual channel circuit based on the update pointer value;
update the next-entry pointer for the terminal buffer memory circuit of the corresponding sequence of buffer memory circuits of the first virtual channel circuit based on the update ID value; and
monitor usage of the first virtual channel circuit to determine a subsequent reprogramming of the first virtual channel circuit.

3. The buffer memory pool circuitry of claim 2 , wherein the processor circuitry is further configured to update the next-entry pointer for the initial buffer memory circuit of the corresponding sequence of buffer memory circuits for the second virtual channel circuit based on the update of the start pointer for the second virtual channel circuit.

4. The buffer memory pool circuitry of claim 1 , wherein the start pointer for the second virtual channel circuit corresponds to the entry identifier of the initial buffer memory circuit of the corresponding sequence of buffer memory circuits for the second virtual channel circuit that is subsequent to the corresponding sequence of buffer memory circuits for the first virtual channel circuit.

5. The buffer memory pool circuitry of claim 1 , wherein the corresponding sequence of buffer memory circuits for each of the plurality of virtual channel circuits is implemented as a first-in-first-out (FIFO) buffer.

6. The buffer memory pool circuitry of claim 1 , wherein:
the entry identifier comprises an identifier for a respective buffer memory circuit,
the payload portion comprises a payload of data stored in the respective buffer memory circuit, and
the next-entry pointer comprises an identifier for a next buffer memory circuit in the corresponding sequence of buffer memory circuits.

7. The buffer memory pool circuitry of claim 1 , wherein determining the fault within the corresponding sequence of buffer memory circuits for the first virtual channel circuit comprises determining that a second buffer memory circuit of the corresponding sequence of buffer memory circuits for the first virtual channel circuit is faulted and to be bypassed, wherein updating the next-entry pointer of the buffer memory circuit of the corresponding sequence of buffer memory circuits for the first virtual channel circuit comprises updating the next-entry pointer for the initial buffer memory circuit of the corresponding sequence of buffer memory circuits for the first virtual channel circuit to identify the entry identifier for a next usable buffer memory circuit subsequent to the second buffer memory circuit of the corresponding sequence of buffer memory circuits, and wherein the processor circuitry is further configured to:
update the next-entry pointer for a terminal buffer memory circuit of the corresponding sequence of buffer memory circuits to identify the entry identifier for a new terminal buffer memory circuit of the corresponding sequence of buffer memory circuits; and
update the next-entry pointer for the new terminal buffer memory circuit to identify the entry identifier for the initial buffer memory circuit of the corresponding sequence of buffer memory circuits.

8. The buffer memory pool circuitry of claim 1 , wherein the plurality of buffer memory circuits of the buffer pool circuitry provides a redundancy that is configurable with respect to at least one of a size in a number of buffer memory circuits or a level of the buffer pool circuitry.

9. A method of allocating buffers, the method comprising:
identifying an allocation request for a first virtual channel circuit of a plurality of virtual channel circuits associated with a plurality of buffer memory circuits forming a buffer pool circuitry, each buffer memory circuit configured to store an entry identifier, a payload portion, and a next-entry pointer, each of the plurality of virtual channel circuits associated with a corresponding sequence of buffer memory circuits and comprising a start pointer identifying the entry identifier for an initial buffer memory circuit of the corresponding sequence of buffer memory circuits;
programming the first virtual channel circuit to be associated with the corresponding sequence of buffer memory circuits based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit of the corresponding sequence of buffer memory circuits; and
updating the next-entry pointer of a buffer memory circuit of the corresponding sequence of buffer memory circuits for the first virtual channel circuit, to reprogram the first virtual channel circuit, based on determining a fault within the corresponding sequence of buffer memory circuits for the first virtual channel circuit,
wherein a length of the corresponding sequence of buffer memory circuits of the first virtual channel circuit is defined by the start pointer for a second virtual channel circuit of the plurality of virtual channel circuits subsequent to the first virtual channel circuit.

10. The method of claim 9 , further comprising:
identifying a reprogram request to change an aspect of the first virtual channel circuit and the corresponding sequence of buffer memory circuits;
determining an update pointer value to the start pointer for the second virtual channel circuit and an update ID value to the next-entry pointer for a terminal buffer memory circuit of the corresponding sequence of buffer memory circuits based on the identified reprogram request;
updating the start pointer for the second virtual channel

Assignees

• Xilinx Inc

Inventors

• Srinivasan Krishnan
• Kumar Shishir
• Ahmad Sagheer
• Morshed Abbas
• Gupta Aman

Classifications

• G06F3/0631

  by allocating resources to storage systems · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title