Method for protecting graphene layer during metal etching
US-2025308988-A1 · Oct 2, 2025 · US
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Joy Nicholas patents
Joy Nicholas is listed as an inventor on 30 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Joy Nicholas |
| Total patents | 30 |
| First publication | Dec 6, 2018 |
| Latest publication | Oct 2, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Hard mask protection of metal interconnects
US-2025308897-A1 · Oct 2, 2025 · US
Method of conductive material deposition
US-12417925-B2 · Sep 16, 2025 · US
Protection structure for liner removal
US-2025259891-A1 · Aug 14, 2025 · US
Method for patterning a substrate using photolithography
US-12334391-B2 · Jun 17, 2025 · US
Protection Layer Formation during Plasma Etching Conductive Materials
US-2024371655-A1 · Nov 7, 2024 · US
Methods for etching metal films using plasma processing
US-12057322-B2 · Aug 6, 2024 · US
Method of Conductive Material Deposition
US-2024178003-A1 · May 30, 2024 · US
Method for Patterning a Substrate Using Photolithography
US-2023197505-A1 · Jun 22, 2023 · US
Method for filling recessed features in semiconductor devices with a low-resistivity metal
US-11621190-B2 · Apr 4, 2023 · US
Recent patents
Latest publications not already listed above.
Method of bottom-up metallization in a recessed feature
US-11450562-B2 · Sep 20, 2022 · US
Method of patterning a metal film with improved sidewall roughness
US-11322364-B2 · May 3, 2022 · US
Method of patterning a metal film with improved sidewall roughness
US-2021313192-A1 · Oct 7, 2021 · US
Method for selective etching at an interface between materials
US-11133194-B2 · Sep 28, 2021 · US
Method for filling recessed features in semiconductor devices with a low-resistivity metal
US-2021287936-A1 · Sep 16, 2021 · US
Method for filling recessed features in semiconductor devices with a low-resistivity metal
US-11024535-B2 · Jun 1, 2021 · US
Methods for etching metal films using plasma processing
US-2021118693-A1 · Apr 22, 2021 · US
Method of bottom-up metallization in a recessed feature
US-2021082750-A1 · Mar 18, 2021 · US
Methods to protect nitride layers during formation of silicon germanium nano-wires in microelectronic workpieces
US-10903077-B2 · Jan 26, 2021 · US
Platform and method of operating for integrated end-to-end CMP-less interconnect process
US-10861744-B2 · Dec 8, 2020 · US
Method for Selective Etching at an Interface Between Materials
US-2020266070-A1 · Aug 20, 2020 · US
Method of protecting low-K layers
US-10734278-B2 · Aug 4, 2020 · US
Ruthenium metal feature fill for interconnects
US-10700009-B2 · Jun 30, 2020 · US
Method for filling recessed features in semiconductor devices with a low-resistivity metal
US-2020118871-A1 · Apr 16, 2020 · US
Method of integrated circuit fabrication with dual metal power rail
US-10580691-B2 · Mar 3, 2020 · US
Methods to protect nitride layers during formation of silicon germanium nano-wires in microelectronic workpieces
US-2020027736-A1 · Jan 23, 2020 · US
Method of Protecting Low-K Layers
US-2019385906-A1 · Dec 19, 2019 · US
Platform and method of operating for integrated end-to-end cmp-less interconnect process
US-2019295887-A1 · Sep 26, 2019 · US
Ruthenium metal feature fill for interconnects
US-2019103363-A1 · Apr 4, 2019 · US
Method of integrated circuit fabrication with dual metal power rail
US-2018350665-A1 · Dec 6, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Tokyo Electron Ltd | 30 |
| IBM | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/056 | 17 |
| H10P50/267 | 16 |
| H10W20/077 | 12 |
| H10P50/71 | 12 |
| H01L21/32136 | 12 |