Platform and method of operating for integrated end-to-end CMP-less interconnect process

US10861744B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10861744-B2
Application numberUS-201916356272-A
CountryUS
Kind codeB2
Filing dateMar 18, 2019
Priority dateMar 20, 2018
Publication dateDec 8, 2020
Grant dateDec 8, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.

First claim

Opening claim text (preview).

What we claim: 1. A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules, the integrated sequence of processing steps comprising: receiving the workpiece into the common manufacturing platform, the workpiece having an upper planar surface and at least one recessed feature therein; depositing a fill material onto the workpiece in one of the one or more film-forming modules hosted on the common manufacturing platform such that the fill material is deposited into the recessed feature; etching the workpiece in one of the one or more etching modules hosted on the common manufacturing platform to remove any fill material deposited on the upper planar surface and to leave behind the fill material in the recessed feature; and obtaining measurement data to determine if the fill material in the recessed feature is coplanar with the upper planar surface, or to determine if the fill material has been removed from the upper planar surface, or both, and repeating the depositing, etching, and measuring until the fill material in the recessed feature is coplanar with the upper planar surface, wherein the obtaining measurement data is performed in a workpiece measurement region located within a dedicated area of at least one of the one or more transfer modules or within a metrology module hosted on the common manufacturing platform, wherein the integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment, and wherein the one or more transfer modules are used to transfer the workpiece between the plurality of processing modules while maintaining the workpiece within the controlled environment, wherein depositing the fill material comprises conformally depositing a conformal layer of the fill material along the upper planar surface and along sidewall surfaces and a bottom surface of the recessed feature, and wherein etching the workpiece includes removing the conformal layer from at least the upper planar surface while leaving the conformal layer on the bottom surface. 2. The method of claim 1 , wherein the controlled environment includes a vacuum environment, an inert gas atmosphere, or a combination thereof. 3. The method of claim 1 , wherein the workpiece measurement region is located in at least one of the one or more transfer modules. 4. The method of claim 1 , wherein the workpiece measurement region is located in the metrology module or the etching module. 5. The method of claim 1 , further comprising: using an intelligence system hosted on the common manufacturing platform, and controlling the integrated sequence of processing steps executed on the common manufacturing platform based on the determination of whether the recess is filled. 6. The method of claim 1 , wherein obtaining the measurement data includes: directing an optical beam from at least one optical source incident on a measurement surface of the workpiece; and receiving an optical signal scattered from the measurement surface of the workpiece into at least one detector. 7. The method of claim 1 , wherein the integrated sequence of processing steps is executed without chemical-mechanical planarization of the upper planar surface. 8. The method of claim 1 , wherein the common manufacturing platform includes at least two deposition modules, at least two metrology modules, and at least two etching modules. 9. The method of claim 1 , wherein the fill material is ruthenium, tungsten, cobalt, nickel, molybdenum, aluminum, niobium, titanium, copper, or a combination thereof. 10. A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules, the integrated sequence of processing steps comprising: receiving the workpiece into the common manufacturing platform, the workpiece having an upper planar surface and at least one recessed feature therein; depositing a fill material onto the workpiece in one of the one or more film-forming modules hosted on the common manufacturing platform such that the fill material is deposited into the recessed feature; etching the workpiece in one of the one or more etching modules hosted on the common manufacturing platform to remove any fill material deposited on the upper planar surface and to leave behind the fill material in the recessed feature; and repeating the depositing, etching, and measuring until the fill material in the recessed feature is coplanar with the upper planar surface, wherein the integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment, and wherein the one or more transfer modules are used to transfer the workpiece between the plurality of processing modules while maintaining the workpiece within the controlled environment, wherein depositing the fill material comprises conformally depositing a conformal layer of the fill material along the upper planar surface and along sidewall surfaces and a bottom surface of the recessed feature, and wherein etching the workpiece includes removing the conformal layer from at least the upper planar surface while leaving the conformal layer on the bottom surface. 11. A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules, the integrated sequence of processing steps comprising: receiving the workpiece into the common manufacturing platform, the workpiece having an upper planar surface and at least one recessed feature therein; depositing a fill material onto the workpiece in one of the one or more film-forming modules hosted on the common manufacturing platform such that the fill material is deposited into the recessed feature; etching the workpiece in one of the one or more etching modules hosted on the common manufacturing platform to remove any fill material deposited on the upper planar surface and to leave behind the fill material in the recessed feature; and obtaining measurement data to determine if the fill material in the recessed feature is coplanar with the upper planar surface, or to determine if the fill material has been removed from the upper planar surface, or both, and repeating the depositing, etching, and measuring until the fill material in the recessed feature is coplanar with the upper planar surface, wherein the obtaining measurement data is performed in a workpiece measurement region located within a dedicated area of at least one of the one or more transfer modules or within a metrology module hosted on the common manufacturing platform, wherein the integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment, and wherein the one or more transfer modules are used to transfer the workpiece between the plurality of processing modules while maintaining the workpiece within the controlled environment, wherein depositing the fill material comprises selectively depositing the fill m

Assignees

Inventors

Classifications

  • by forming self-aligned vias · CPC title

  • comprising a chamber adapted to a particular process · CPC title

  • Apparatus for fluid treatment (H10P72/0441, H10P72/0448 take precedence) · CPC title

  • Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • characterised by movements or sequence of movements of transfer devices · CPC title

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What does patent US10861744B2 cover?
A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufactur…
Who is the assignee on this patent?
Tokyo Electron Ltd
What technology area does this patent fall under?
Primary CPC classification H10P72/0461. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 08 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).