Method for filling recessed features in semiconductor devices with a low-resistivity metal

Patent metadata

Field	Value
Publication number	US-11024535-B2
Application number	US-201916598772-A
Country	US
Kind code	B2
Filing date	Oct 10, 2019
Priority date	Oct 10, 2018
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature;
pre-treating the patterned substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer;
depositing a metal layer on the patterned substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature;
removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature; and
repeating the pre-treating, depositing and removing at least once to increase a thickness of the metal layer in the recessed feature.

2. The method of claim 1 , wherein the pre-treating includes forming self-assembled monolayers (SAMs) on the first layer.

3. The method of claim 1 , wherein the metal layer is selected from the group consisting of Ru metal, Co metal, and W metal, and the second layer is selected from the group consisting of Cu metal, Ru metal, Co metal, W metal, and a combination thereof.

4. The method of claim 1 , wherein the first layer includes a dielectric material and the second layer includes an initial metal layer.

5. The method of claim 1 , wherein the pre-treating includes exposing the patterned substrate to a silicon-containing gas.

6. The method of claim 5 , wherein the silicon-containing gas includes an alkyl silane, an alkoxysilane, an alkyl alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an alkyl alkoxysiloxane, an aryl silane, an acyl silane, an aryl siloxane, an acyl siloxane, a silazane, or combination thereof.

7. The method of claim 5 , wherein the silicon-containing gas includes dimethylsilane dimethylamine (DMSDMA), trimethylsilane dimethylamine (TMSDMA), or bis(dimethylamino) dimethylsilane (BDMADMS).

8. The method of claim 5 , wherein the silicon-containing gas includes N,O-bistrimethylsilyltrifluoroacetamide (BSTFA) or trimethylsilyl-pyrrole (TMS-pyrrole).

9. The method of claim 1 , wherein the removing includes reactive ion etching (RIE).

10. The method of claim 1 , wherein the removing includes exposing the patterned substrate to plasma-excited etching gas containing O 2 gas and optionally a halogen-containing gas.

11. A method of forming a semiconductor device, the method comprising:
providing a patterned substrate containing a recessed feature formed in a first layer containing a dielectric material and a second layer containing an initial metal layer that is exposed in the recessed feature;
pre-treating the patterned substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, wherein the surface modifier adsorbs on a sidewall of the first layer in the recessed feature;
depositing a ruthenium (Ru) metal layer on the patterned substrate by vapor phase deposition using a gaseous exposure of Ru 3 (CO) 12 and carbon monoxide (CO), wherein the Ru metal layer is preferentially deposited on the second layer in the recessed feature;
removing Ru metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the Ru metal layer on the second layer in the recessed feature; and
repeating the pre-treating, depositing and removing at least once to increase a thickness of the Ru metal layer on the initial metal layer in the recessed feature.

12. The method of claim 11 , wherein the pre-treating includes exposing the patterned substrate to a silicon-containing gas.

13. The method of claim 12 , wherein the silicon-containing gas includes an alkyl silane, an alkoxysilane, an alkyl alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an alkyl alkoxysiloxane, an aryl silane, an acyl silane, an aryl siloxane, an acyl siloxane, a silazane, or combination thereof.

14. The method of claim 12 , wherein the silicon-containing gas includes dimethylsilane dimethylamine (DMSDMA), trimethylsilane dimethylamine (TMSDMA), or bis(dimethylamino) dimethylsilane (BDMADMS).

15. The method of claim 11 , wherein the removing includes reactive ion etching (RIE).

16. The method of claim 11 , wherein the removing includes exposing the patterned substrate to plasma-excited etching gas containing O 2 gas and optionally a halogen-containing gas.

17. A method of forming a semiconductor device, the method comprising:
providing a patterned substrate containing a recessed feature formed in a first layer containing a dielectric material and a second layer containing an initial metal layer that is exposed in the recessed feature;
pre-treating the patterned substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, wherein the surface modifier includes a silicon-containing gas that adsorbs on a sidewall of the first layer in the recessed feature;
depositing a ruthenium (Ru) metal layer on the substrate by vapor phase deposition using a gaseous exposure of a Ru-containing precursor, where the Ru metal layer is preferentially deposited on the second layer in the recessed feature;
removing, by reactive ion etching (RIE), Ru metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the Ru metal layer on the second layer in the recessed feature; and
repeating the pre-treating, depositing and removing at least once to fully fill the recessed feature with Ru metal.

18. The method of claim 17 , wherein the silicon-containing gas includes dimethylsilane dimethylamine (DMSDMA), trimethylsilane dimethylamine (TMSDMA), or bis(dimethylamino) dimethylsilane (BDMADMS).

19. The method of claim 17 , wherein the Ru-containing precursor includes Ru 3 (CO) 12 , (2,4-dimethylpentadienyl) (ethylcyclopentadienyl) ruthenium (Ru(DMPD)(EtCp)), bis(2,4-dimethylpentadienyl) ruthenium (Ru(DMPD) 2 ), 4-dimethylpentadienyl) (methylcyclopentadienyl) ruthenium (Ru(DMPD)(MeCp)), or bis(ethylcyclopentadienyl) ruthenium (Ru(EtCp) 2 ).

Assignees

• Tokyo Electron Ltd

Inventors

• Yu Kai-Hung
• O'Meara David
• Joy Nicholas
• Pattanaik Gyanaranjan
• Clark Robert
• Tapily Kandabara
• HAKAMATA Takahiro
• Wajda Cory
• Leusink Gerrit

Classifications

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title

• H10P14/36

  characterised by treatments done before the formation of the materials · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10P14/20

  of semiconductor materials · CPC title