Method of protecting low-K layers

Patent metadata

Field	Value
Publication number	US-10734278-B2
Application number	US-201916436687-A
Country	US
Kind code	B2
Filing date	Jun 10, 2019
Priority date	Jun 15, 2018
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A process is provided in which low-k layers are protected from etch damage by the use of a selectively formed protection layer which forms on the low-k layer. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. In one embodiment, the selectively formed protection layer may be formed by a selective deposition process which selectively forms layers on the low-k dielectric but not over the conductor layer. The selectively formed protection layer may then be utilized to protect the low-k layer from a plasma etch that is utilized to recess the conductor. In this manner, a conductor (for example metal) may be recessed in a low-k dielectric layer via a plasma etch process.

First claim

What is claimed is:

1. A method for processing a substrate, the method comprising:
providing the substrate with a patterned structure comprising a conductor layer and a low-k layer;
forming a self-aligned monolayer on exposed surfaces of the conductor layer;
performing a selective deposition of a protection layer, the selective deposition selectively forming a protection layer on the low-k layer; and
performing a conductor recess dry etch to selectively remove the self-aligned monolayer and a portion of the conductor layer, wherein the protection layer suppresses damage to the low-k layer during the conductor recess dry etch.

2. The method of claim 1 , further comprising:
providing a barrier or liner layer between the conductor layer and the low-k layer, wherein the conductor recess dry etch selectively etches the conductor layer to the barrier or liner layer so that the barrier or liner layer suppresses damage to sidewalls of the low-k layer during the conductor recess dry etch.

3. The method of claim 1 , further comprising:
providing a barrier or liner layer between the conductor layer and the low-k layer; and
performing, after the conductor recess dry etch, a barrier or liner layer removal process to remove an exposed portion of the barrier or liner layer.

4. The method of claim 3 , further comprising:
forming an etch stop layer on the substrate after performing the conductor recess dry etch, wherein the protection layer is on the substrate during the forming of the etch stop layer.

5. The method of claim 3 , further comprising:
forming an etch stop layer on the substrate after performing the conductor recess dry etch, wherein the protection layer is removed from the substrate before the forming of the etch stop layer.

6. The method of claim 1 , further comprising:
forming an etch stop layer on the substrate after performing the conductor recess dry etch, wherein the protection layer is on the substrate during the forming of the etch stop layer.

7. The method of claim 1 , further comprising:
forming an etch stop layer on the substrate after performing the conductor recess dry etch, wherein the protection layer is removed from the substrate before the forming of the etch stop layer.

8. The method of claim 1 , wherein suppression of damage to the low-k layer suppresses increases in a dielectric constant of the low-k layer.

9. A method utilized in forming a self-aligned via, the method comprising:
providing a substrate with a patterned structure comprising a conductor layer and a low-k dielectric layer, the conductor layer being embedded in the low-k dielectric layer, and the conductor layer being a lower conductor layer to which the self-aligned via will be located over;
performing a selective formation of a protection layer, the selective formation selectively forming the protection layer over the low-k dielectric layer and not over the conductor layer; and
performing a conductor recess dry etch to selectively remove a portion of the conductor layer, wherein the protection layer suppresses damage to the low-k dielectric layer during the conductor recess dry etch.

10. The method of claim 9 , further comprising forming a self-aligned monolayer on exposed surfaces of the conductor layer before the selective formation of the protection layer.

11. The method of claim 9 , further comprising:
forming an etch stop layer on the substrate after performing the conductor recess dry etch, wherein the protection layer is on the substrate during the forming of the etch stop layer.

12. The method of claim 9 , further comprising:
forming an etch stop layer on the substrate after performing the conductor recess dry etch, wherein the protection layer is removed from the substrate before the forming of the etch stop layer.

13. The method of claim 9 , further comprising, after the conductor recess dry etch, leaving the protection layer on the substrate during one or more additional self-aligned via process steps.

14. The method of claim 9 , further comprising removing the protection layer after the conductor recess dry etch.

15. The method of claim 9 , wherein suppression of damage to the low-k dielectric layer suppresses increases in a dielectric constant of the low-k dielectric layer.

16. A method utilized in forming a recess in a metal layer, the method comprising:
providing a substrate with a patterned structure comprising a metal layer and a low-k dielectric layer, the metal layer being embedded in the low-k dielectric layer, the metal layer having a plurality of exposed metal surfaces and the low-k dielectric layer having a plurality of low-k dielectric exposed surfaces;
performing a selective formation of a protection layer, the selective formation selectively forming the protection layer over the plurality of low-k dielectric exposed surfaces; and
performing a metal recess dry etch to remove a portion of the metal layer, thereby forming a recess in the metal layer, wherein the protection layer suppresses damage to the low-k dielectric layer during the metal recess dry etch.

17. The method of claim 16 , wherein the metal layer comprises ruthenium and the metal recess dry etch comprises an oxygen containing plasma.

18. The method of claim 16 , further comprising forming a self-aligned monolayer on the plurality of exposed metal surfaces before the selective formation of the protection layer.

19. The method of claim 16 , further comprising removing the protection layer after performing the metal recess dry etch.

20. The method of claim 16 , further comprising leaving the protection layer on the substrate during one or more additional process steps performed after the recess is formed.

Assignees

• Tokyo Electron Ltd

Inventors

• Aizawa Hirokazu
• Pillai Karthikeyan
• Joy Nicholas
• Tapily Kandabara

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/267

  using plasmas · CPC title

• H10P50/71 Primary

  using masks for conductive or resistive materials · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title