Chip for performing contactless chip test and method for performing contactless chip test on input/output driver
US-2026009844-A1 · Jan 8, 2026 · US
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Hsu Ying-Yu patents
Hsu Ying-Yu is listed as an inventor on 35 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hsu Ying-Yu |
| Total patents | 35 |
| First publication | Jan 1, 2015 |
| Latest publication | Jan 8, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Minimum intrinsic timing utilization auto alignment on multi-die system
US-11569805-B2 · Jan 31, 2023 · US
Minimum intrinsic timing utilization auto alignment on multi-die system
US-2022294435-A1 · Sep 15, 2022 · US
Stacked chip layout
US-11188701-B2 · Nov 30, 2021 · US
Stacked chip layout
US-2020151381-A1 · May 14, 2020 · US
Stacked chip layout and method of making the same
US-10540473-B2 · Jan 21, 2020 · US
Transceiver and clock generation module
US-10447466-B2 · Oct 15, 2019 · US
Transceiver and clock generation module
US-2019222410-A1 · Jul 18, 2019 · US
Stacked chip layout and method of making the same
US-2019095572-A1 · Mar 28, 2019 · US
Stacked chip layout having overlapped regions
US-10162926-B2 · Dec 25, 2018 · US
Recent patents
Latest publications not already listed above.
Delay signal generating apparatus using glitch free digitally controlled delay line and associated delay signal generating method
US-10158352-B2 · Dec 18, 2018 · US
Delay signal generating apparatus using glitch free digitally controlled delay line and associated delay signal generating method
US-2018198439-A1 · Jul 12, 2018 · US
Data sampling alignment method for memory interface
US-9965409-B2 · May 8, 2018 · US
On-chip eye diagram capture
US-9766288-B2 · Sep 19, 2017 · US
Semiconductor device for simultaneous operation at two temperature ranges
US-9748241-B2 · Aug 29, 2017 · US
Data sampling alignment method for memory interface
US-2017192913-A1 · Jul 6, 2017 · US
Data sampling alignment method for memory inferface
US-9619409-B2 · Apr 11, 2017 · US
Supply boost device
US-9564900-B2 · Feb 7, 2017 · US
Stacked chip layout and method of making the same
US-2017032072-A1 · Feb 2, 2017 · US
System and method for calibrating chips in a 3D chip stack architecture
US-9503061-B2 · Nov 22, 2016 · US
Method of making stacked chip layout
US-9495500-B2 · Nov 15, 2016 · US
Supply boost device
US-2016308533-A1 · Oct 20, 2016 · US
Semiconductor device for simultaneous operation at two temperature ranges
US-2016254260-A1 · Sep 1, 2016 · US
Driver circuit
US-9419615-B2 · Aug 16, 2016 · US
Driver circuit
US-2016211848-A1 · Jul 21, 2016 · US
System and method for aligning data bits
US-9363115-B2 · Jun 7, 2016 · US
On-chip eye diagram capture
US-2016131708-A1 · May 12, 2016 · US
System and method for calibrating chips in a 3d chip stack architecture
US-2016118960-A1 · Apr 28, 2016 · US
On-chip eye diagram capture
US-9267988-B2 · Feb 23, 2016 · US
Method of making stacked chip layout
US-2016004807-A1 · Jan 7, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 23 |
| Mediatek Inc | 7 |
| Taiwan Semiconductor Mfg | 5 |
| Hsu Ying-Yu | 1 |
| Sheen Ruey-Bin | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/297 | 14 |
| H10W90/00 | 14 |
| G06F1/10 | 12 |
| H01L25/0657 | 12 |
| H10W90/288 | 10 |