Minimum intrinsic timing utilization auto alignment on multi-die system

Patent metadata

Field	Value
Publication number	US-11569805-B2
Application number	US-202117548571-A
Country	US
Kind code	B2
Filing date	Dec 12, 2021
Priority date	Mar 15, 2021
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

The present invention provides a system including a transmitter and a receiver is disclosed. The transmitter includes a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals, the first main strobe path is configured to generate a first strobe signal, and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced. The receiver includes a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal to generate a plurality of second strobe signals, and the second main data path is configured to receive the plurality of data signals, and uses the plurality of second strobe signals to sample the plurality of data signals to generate a plurality of sampled signals, respectively.

First claim

What is claimed is:

1. A system, comprising:
a transmitter, comprising a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals, the first main strobe path is configured to generate a first strobe signal, the first main data path comprises a first delay circuit, the first main strobe path comprises a second delay circuit, and a delay amount of the first main data path and a delay amount of the first main strobe path are unbalanced so that the strobe signal and the plurality of data signals are not aligned; and
a receiver, comprising a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal to generate a plurality of second strobe signals, and the second main data path is configured to receive the plurality of data signals, and uses the plurality of second strobe signals to sample the plurality of data signals to generate a plurality of sampled signals, respectively;
a deskew circuit, configured to generate a first control signal and a second control signal to control the delay amount of the first delay circuit and the second delay circuit, respectively.

2. The system of claim 1 , wherein the system comprises a first die and a second die, the transmitter is within the first die, and the receiver is within the second die.

3. The system of claim 1 , wherein the first main data path comprises:
the first delay circuit, configured to receive a first reference clock signal to generate a delayed first reference clock signal;
a clock tree synthesizer, configured to receive the delayed reference clock signal to generate a plurality of first clock signals; and
a plurality of first serializers, configured to use the plurality of first clock signals to sample input signals to generate the plurality of data signals; and
the first main strobe path comprises:
the second delay circuit, configured to receive a second reference clock signal to generate a second clock signal;
a second serializer, configured to receive the second clock signal to generate the strobe signal.

4. The system of claim 3 , wherein there is no clock tree synthesizer between the second delay circuit and the second serializer.

5. The system of claim 1 , wherein delay amount of the second main data path and delay amount of the second main strobe path are unbalanced.

6. The system of claim 5 , wherein the second main strobe path comprises:
a strobe signal generator and a clock tree synthesizer, configured to receive the strobe signal to generate a plurality of second strobe signals; and
the second main data path comprises:
a sampling circuit, configured to use the plurality of second strobe signals to sample the plurality of data signals to generate the plurality of sampled signals, respectively.

7. The system of claim 6 , wherein there is no clock tree synthesizer positioned in the second main data path.

8. The system of claim 1 , wherein the deskew circuit comprises a first data path, a first strobe path, a second data path and a second strobe path; the first data path comprises a third delay circuit whose delay amount is twice that of the first delay circuit within the first main data path, the first strobe path comprises a fourth delay circuit whose delay amount is twice that of the second delay circuit within the first main strobe-path.

9. The system of claim 8 , wherein the second data path is configured to receive a first signal generated by the first data path, the second strobe path is configured to receive a second signal generated by the first strobe path, and the second data path comprises a phase comparator to compare phases of the first signal and the second signal to generate a phase detection result; and
the deskew circuit further comprises a control circuit to generate the first control signal and the second control signal according to the phase detection result, wherein the first control signal is used to control the first delay circuit and the third delay circuit, and the second control signal is used to control the second delay circuit and the fourth delay circuit.

10. The system of claim 9 , wherein the system comprises a first die and a second die, the transmitter is within the first die, the receiver is within the second die, the first data path and the first strobe path of the deskew circuit are within the first die, and the second data path and the second strobe path of the deskew circuit are within the second die.

Assignees

• Mediatek Inc

Inventors

• Hsu Ying-Yu

Classifications

• H04L7/0033

  Correction by delay · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H03K5/131 Primary

  Digitally controlled · CPC title

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title